Overview

Cadence® Denali® silicon-proven GDDR6 PHY and controller IP showcase leading-edge BER, BIST, and RAS capabilities. GDDR6 offers significantly more performance than the fastest speed of DDR5 at a moderate cost, making it ideal for high-bandwidth applications. Cadence’s unique, single-vendor GDDR6 IP solution speeds up integration and reduces interoperability risk.

gddr-phy

Key Benefits

Proven

Silicon characterization reports available in multiple process technologies and foundries

Low Latency

For data-intensive applications

Low Power and Area

Industry-leading PPA based on advanced architecture and implementation

Low BER

Supporting standard PCB materials

Reliable

Maximum system margin with advanced clocking and I/O architectures

Future proof

Cutting edge technology with the latest GDDR protocols and the highest data rates

Features

  • Single configuration supports one GDDR6 device per channel (coplanar) or two GDDR6 devices per channel (clamshell)
  •  DFI PHY Independent Mode for initialization and training
  • Adaptive and continuous timing recovery
  •  Internal and external datapath loop-back modes
  •  Transmit crosstalk cancelation of immediate neighbors
  •  Per-bit DFE, CTLE, and FFE equalization

 

  • In-line SEC/DED ECC
  • Supports advanced RAS features including error scrubbing, parity, etc.
  • Compatible with GDDR6 devices compliant to JESD250b
  • Single and multi-port host options for Arm® AMBA®4, AMBA 3 AXI, and low-latency Denali interfaces
  • QoS features allow command prioritization
  • Flexible paging policy
  • Memory controller interface is based on DFI 5.0
  • The controller runs at 1/8 of the memory clock speed for ease of timing closure