Demonstrating electrical-thermal co-simulation with Celsius Thermal Solver
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Key Benefits
- Accurate thermal modeling of SoC with Voltus/Celsius integration
- Thermal-aware electronic designs with integration of Celsius with Virtuoso, AWR, and OrbitIO
- Reduces cost and time by identifying potential problems early with both pre-route and post-route
- Ensures reliable power delivery by verifying AC, DC, and power-ripple analysis
- Optimizes a PDN across the board/package interface
- Easily addresses system-level power analysis challenges with a block-based schematic editor
To help you quickly validate the sufficiency, efficiency, and stability of the power delivery network (PDN), Cadence® Celsius™ Advanced PTI allows power terminal integrity (PTI) experts to perform PDN verification from each power source to each sink across multiple boards and packages.
Cadence Allegro® PowerTree™ technology lets you set up the analysis before the physical design process and validate the bill of materials defined during the logical design stage. As the physical implementation proceeds, the set-up captured in the PowerTree environment can be reused, essentially making DC and AC power integrity analysis a push-button process at each design stage.
Figure 1: Accurately simulate problematic real-world structures such as cutouts, via fields, wire bonds, and neck downs
Thermal-Aware DC Analysis
Celsius PowerDC™ technology provides an efficient DC analysis for signoff of IC package and PCB designs, including electrical/thermal co-simulation to maximize accuracy. Celsius PowerDC technology quickly pinpoints excessive IR drop along with areas of excess current density and thermal hotspots to minimize your design’s risk of field failure.
AC Analysis
Sigrity OptimizePI™ technology does a complete AC frequency analysis of boards and IC packages. Supporting both pre-and post-layout studies, it quickly pinpoints the best decap selections and placement locations to meet your PDN needs at the lowest possible cost. PDN impedance profiles are checked against target impedance constraints to ensure that the design meets PDN specifications.
Power-Ripple Analysis
The power ground noise simulation workflow from Sigrity SPEED2000™ technology can be used for direct time-domain power/ground noise simulation for the I/O power supply. Instead of having to extract S-parameter models and use them in a SPICE simulation, Sigrity Advanced PI provides a straightforward time-domain power integrity approach for either a PCB or IC package. It delivers a stable simulation result that would otherwise be more time consuming to obtain.
Sigrity Topology Explorer
This general-purpose topology exploration function can be used for exploring power topologies across multiple fabrics. By connecting the power ports of chip, package, and boards, you can create and simulate complete source-to-sink connectivity. PDN models for each fabric, created using the Sigrity PowerSI™ or Cadence Clarity™ 3D Solver, are excited using a model for the voltage regulator module (VRM). The resulting signal provides a time-domain view of the PDN voltage at each critical point from source to sink. You can determine if any portion of the PDN generates problems delivering power within the system specification.
Figure 2: The intuitive Sigrity topology explorer user experience makes it easy to join interconnect models for the PDN
across multiple boards, as well as chip and package, and see the impact to power stability
across multiple boards, as well as chip and package, and see the impact to power stability
Features
- Automatically set up DC simulations using PowerTree data (source/sink definitions) captured at the schematic stage of the design process
- Identifies difficult-to-locate, highly resistive routing neck-downs and finds the one via among thousands that will fail under stress
- Determines if it is possible to reduce plane layers without adding DC or thermal reliability risk
- Reduces PDN cost for new designs and post-production products
- Intuitive and interactive visualization of PDN performance
