The first high-level synthesis platform for use across your entire SoC design, Cadence® Stratus™ High-Level Synthesis (HLS) delivers up to 10X better productivity than traditional RTL design. Based on more than 14 years of production HLS deployment, the Stratus tool lets you quickly design and verify high-quality RTL implementations from abstract SystemC, C, or C++ models. Using the platform, you can reduce the intellectual property (IP) development cycle from months to weeks.
With Stratus HLS, you can easily create abstract models using its integrated design environment (IDE) and synthesize optimized hardware from those models. You can then retarget these models to new technology platforms and reuse them more easily than you could traditional hand-coded RTL. You can actively make tradeoffs between power, area, and performance from within the HLS environment.
Users have reported productivity as high as 2 million verified gates/designer/year, compared to 200,000 with the traditional RTL flow. For more details, read the Stratus HLS datasheet.
Hear how in only three months Ph. D student Myung-Seok Shim was able to learn how to take a TensorFlow machine learning model for image recognition to RTL using Stratus High-Level Synthesis.
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With our high-level synthesis flow and the Stratus platform, we're now doing the kinds of things that we couldn't have imagined doing previously.
Ray McConnell, CTO, Blu Wireless Technology
Our highly integrated 100Gbps transport systems operate at very high frequency, which presented a major design challenge. By designing at a higher level of abstraction in SystemC, our design team was able to implement the customized hardware much more quickly and effectively.
Masao Nakano, Design Engineer, Device Development Department, Network Products Division, Fujitsu Kansai-Chubu Net-Tech
Using [the] HLS design flow we got an average 35% better performance with up to 51% less power and up to 38% less area than hand-edited RTL.
Masato Tatsuoka, Socionext Inc.
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