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  • PRODUCTS
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • Logic Equivalence Checking
        • Innovus Implementation and Floorplanning
        • Functional ECO
        • Low-Power Validation
        • Synthesis
        • Power Analysis
        • Constraints and CDC Signoff
        • Silicon Signoff and Verification
        • Library Characterization
        • Test
        • Flows
      • Custom IC / Analog / RF Design
        • Circuit Design
        • Circuit Simulation
        • Layout Design
        • Layout Verification
        • Library Characterization
        • RF / Microwave Solutions
        • Flows
      • System Design and Verification
        • Debug Analysis
        • Emulation
        • Formal and Static Verification
        • FPGA-Based Prototyping
        • Planning and Management
        • Simulation
        • Software-Driven Verification
        • Verification IP
        • System-Level Verification IP
        • Flows
      • IP
        • Interface IP
        • Denali Memory IP
        • Tensilica Processor IP
        • Analog IP
        • System / Peripherals IP
        • Verification IP
      • IC Package Design and Analysis
        • Cross-Platform Co-Design and Analysis
        • IC Package Design
        • SI/PI Analysis
        • SI/PI Analysis Point Tools
        • Flows
    • SYSTEM INNOVATION
      • System Analysis
        • Electromagnetic Solutions
        • RF / Microwave Design
        • Thermal Solutions
        • System Analysis Resources Hub
      • Embedded Software
      • PCB Design and Analysis
        • Design Authoring
        • PCB Layout
        • Library and Design Data Management
        • Analog/Mixed-Signal Simulation
        • SI/PI Analysis
        • SI/PI Analysis Point Tools
        • What's New in Allegro
        • What's New in Sigrity
        • RF / Microwave Design
        • Flows
        • Advanced PCB Design & Analysis Blog
        • Augmented Reality Lab Tools
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      • AI IP Portfolio
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Stratus High-Level Synthesis

Cuts IP development from months to weeks

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Key Benefits

  • 10X faster time to high-quality RTL
  • Up to 50% lower power
  • Up to 25% less area
  • Easy design closure

With Cadence® Stratus™ High-Level Synthesis (Stratus HLS), engineering teams can quickly design and verify high-quality RTL implementations from abstract IEEE 1666 synthesizable SystemC®, C, or C++ models. The models can be easily created using the Stratus integrated design environment (IDE). Stratus synthesizable IP for SystemC provides simulation and synthesis models for common bus-based and point-to-point communication protocols as well as common mathematical operations and datatypes.​

Leveraging the Genus™ Synthesis and Joules™ RTL Power engines inside of Stratus HLS, the power, performance, and area (PPA) results are typically equal to or better than those achieved with hand-written RTL. Front-end designers get high-quality PPA estimates through turnkey integration with the Cadence digital flow.​

With Stratus HLS, SystemC models can be retargeted to new technology platforms and reused more easily than traditional hand-coded RTL. The Stratus graphical user interface (GUI) and Tcl API also allow designers to quantitatively evaluate tradeoffs between the PPA from within the high-level synthesis environment. ​

Stratus HLS automates the design and verification flow of hundreds of blocks from transaction-level modeling (TLM) to gates. In addition, Stratus HLS helps with the real-world issues of engineering change orders (ECOs) and routability, both of which normally occur much later in the flow, through tight integration with the full Cadence tool flow.

ASK US A QUESTION

 

Users have reported productivity as high as 2 million verified gates/designer/year, compared to 200,000 with the traditional RTL flow. For more details, read the Stratus HLS datasheet.

file

Contact Us

TRAINING COURSES

WEBINAR

AI Accelerator Design
with Stratus™ HLS
(sign-in required)

VIEW WEBINAR

Hear how in only three months Ph. D student Myung-Seok Shim was able to learn how to take a TensorFlow machine learning model for image recognition to RTL using Stratus High-Level Synthesis.

  • Related Products

    • Genus Synthesis Solution
    • Joules RTL Power Solution
  • Related Links

    • How High-Level Synthesis Was Used to Develop an Image-Processing IP Design from C++ Source Code White Paper
    • Using High-Level Synthesis to Design and Verify 802.11ah Baseband IP White Paper
    • How the Productivity Advantages of High-Level Synthesis Can Improve IP Design, Verification, and Reuse White Paper
Videos

EEJournal Chalk Talk: TensorFlow to RTL with High-Level Synthesis

Designing a “First-Time-Right” Wi-Fi HaLow Baseband in less than 6 Months

From TensorFlow to RTL in three months

Designing an Automotive Graphics Display Controller with Stratus HLS

A High Level Synthesis (HLS) Design Flow for Scaling to Multiple IP, SoC, and Process Targets

Whiteboard Wednesdays - TensorFlow to RTL with High-Level Synthesis

News ReleasesVIEW ALL
  • Cadence to Acquire NUMECA to Expand System Analysis Capabilities with Computational Fluid Dynamics 01/20/2021

  • Cadence Announces Fourth Quarter and Fiscal Year 2020 Financial Results Webcast 01/08/2021

  • Samsung Foundry Certifies Cadence System Analysis and Advanced Packaging Design Tool Flow for 2.5/3D Chip Designs 12/16/2020

  • Samsung Foundry Adopts Spectre X Simulator for 5nm Design 12/08/2020

  • Rockley Photonics Collaborates with Cadence to Create a High-Performance System for Hyperscale Data Centers 12/02/2020

Blogs VIEW ALL
Customers

With our high-level synthesis flow and the Stratus platform, we're now doing the kinds of things that we couldn't have imagined doing previously.

Ray McConnell, CTO, Blu Wireless Technology

Read More or View All Customers

Our highly integrated 100Gbps transport systems operate at very high frequency, which presented a major design challenge. By designing at a higher level of abstraction in SystemC, our design team was able to implement the customized hardware much more quickly and effectively.

Masao Nakano, Design Engineer, Device Development Department, Network Products Division, Fujitsu Kansai-Chubu Net-Tech

Read More or View All Customers

Using [the] HLS design flow we got an average 35% better performance with up to 51% less power and up to 38% less area than hand-edited RTL.

Masato Tatsuoka, Socionext Inc.

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