Stratus High-Level Synthesis

With Cadence® Stratus™ High-Level Synthesis (Stratus HLS), engineering teams can quickly design and verify high-quality RTL implementations from abstract IEEE 1666 synthesizable SystemC®, C, or C++ models. The models can be easily created using the Stratus integrated design environment (IDE). Stratus synthesizable IP for SystemC provides simulation and synthesis models for common bus-based and point-to-point communication protocols as well as common mathematical operations and datatypes.​

Leveraging the Genus™ Synthesis and Joules™ RTL Power engines inside of Stratus HLS, the power, performance, and area (PPA) results are typically equal to or better than those achieved with hand-written RTL. Front-end designers get high-quality PPA estimates through turnkey integration with the Cadence digital flow.​

With Stratus HLS, SystemC models can be retargeted to new technology platforms and reused more easily than traditional hand-coded RTL. The Stratus graphical user interface (GUI) and Tcl API also allow designers to quantitatively evaluate tradeoffs between the PPA from within the high-level synthesis environment. ​

Stratus HLS automates the design and verification flow of hundreds of blocks from transaction-level modeling (TLM) to gates. In addition, Stratus HLS helps with the real-world issues of engineering change orders (ECOs) and routability, both of which normally occur much later in the flow, through tight integration with the full Cadence tool flow.

Users have reported productivity as high as 2 million verified gates/designer/year, compared to 200,000 with the traditional RTL flow. For more details, read the Stratus HLS datasheet.