Overcoming PPA and Productivity Challenges of New Age ICs with Mixed Placement Innovation
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Key Benefits
- Massively parallel architecture for handling large designs and supporting multi-threading on multi-core workstations, as well as distributed processing over networks of computers
- New GigaPlace solver-based placement technology, which is timing, power, and congestion driven with topology-, pin-access-, and color-aware understanding to provide optimal placement, wire length, utilization, and PPA results
- Unique mixed-macro and standard-cell placement capability enabling automated macro locations for ever-increasingly complex floorplans with hundreds of macro cells
- Advanced GigaOpt multi-threaded, layer-aware optimization engine, which is timing and power driven to reduce dynamic and leakage power
- Additional advanced-node technologies, such as via pillars, power integrity-aware placement and optimization, clock skewing for power, continuous congestion monitoring, and optimized routers for handling self-aligned double patterning for better PPA
- Mature hierarchy automation features for large Hierarchical designs like advanced block abstraction, automated partitioning and hierarchical timing closure, along with new floorplan synthesis capabilities
- Innovative machine learning-driven capabilities through the whole implementation flow leading to best PPA results on challenging, high-performance designs
The Cadence® Innovus™ Implementation System is optimized for the most challenging designs, as well as the latest FinFET 16nm, 14nm, 7nm, and 5nm processes, helping you get an earlier design start with a faster ramp-up. With unique new capabilities in placement, optimization, routing, and clocking, the Innovus system features an architecture that accounts for upstream and downstream steps and effects in the design flow. This architecture minimizes design iterations and provides the runtime boost you’ll need to get to market faster. Using the Innovus system, you’ll be equipped to build integrated, differentiated systems with less risk.
The Innovus system features a variety of key capabilities. Its massively parallel architecture can handle large designs and take advantage of multi-threading on multi-core workstations, as well as distributed processing over networks of computers.
Based on the well-established NanoRoute™ engine, next-generation slack and power-driven routing with track-aware timing optimization addresses signal integrity early on and improves post-route correlation. The Innovus system includes full-flow multi-objective technology, which makes concurrent electrical and physical optimization possible. It also shares a customizable flow via a common UI and user commands with synthesis and signoff tools. As a result, you can take advantage of robust reporting and visualization, improving your design efficiency and productivity across the whole digital flow.
With block sizes growing in both cell count and complexity, the number of macros that need to be positioned in the floorplan is exploding. The Innovus system offers mixed-macro and standard-cell placement, which enables macro locations to be automatically generated, reducing the time to create an optimal floorplan from days to hours.
The latest advances in machine learning computer science are very relevant for digital implementation flows. The Innovus system incorporates machine learning technology to deliver the best PPA for the most challenging, high-performance blocks. The designer has complete control over the machine learning training, to ensure it is customized for their specific design requirements.
Cadence’s Genus™ Synthesis Solution is tightly integrated with the Innovus system, which enables a seamless move from RTL synthesis to implementation. With shared placement and optimization technology from the GigaPlace™ and GigaOpt™ engines for Genus physical synthesis, this offers a big benefit for advanced-node design convergence.
As voltage decreases in the latest FinFET process nodes, IR and EM constraints become increasingly important. The Innovus system includes comprehensive power integrity-aware placement, optimization, clock tree, and routing features to ensure IR and EM violations are addressed during implementation without impacting final PPA.
Cadence’s Tempus™ Timing Signoff Solution, Quantus™ Extraction Solution, and Voltus™ IC Power Integrity Solution are integrated with the Innovus system. With this integration, you can accurately model parasitics, timing, signal, and power integrity effects at the early stage of physical implementation, and achieve faster convergence on these electrical metrics, resulting in more efficient design closure.
Resource Library
Video (9)
- Better PPA with Innovus Mixed Placer Technology – Gigaplace XL
- Pushing frequency, power and area with the iSpatial flow to achieve Design Excellence
- GigaPlace Solver-Based Placement Technology In Innovus Implementation System
- Reducing Design Flow Iterations with GigaPlace Engine
- Maximizing PPA on ARM’s Next-Generation High-Performance Processor Using the Latest Cadence Implementation and Signoff Tools/Flow
- Samsung Foundry 14LPP: The Continual Thrust in FinFET Leadership
- eInfochips Shortens Runtime on 300M Gate Count SoCs with Innovus Implementation System
- In Sync with Innovus Technology: Learn how Genus and Innovus technologies are tightly correlated.
- Tackling 16nm Challenges for Arm Cortex-A72 Processor
Demo Videos (5)
- Better PPA with Innovus Mixed Placer Technology – Gigaplace XL
- GigaPlace Solver-Based Placement Technology In Innovus Implementation System
- Reducing Design Flow Iterations with GigaPlace Engine
- In Sync with Innovus Technology: Learn how Genus and Innovus technologies are tightly correlated.
- Tackling 16nm Challenges for Arm Cortex-A72 Processor
Press Releases (5)
- Cadence Extends Digital Design Leadership with Revolutionary ML-based Cerebrus, Delivering Best-in-class Productivity and Quality of Results
- Cadence Achieves Digital and Custom/Analog EDA Flow Certification for TSMC N6 and N5 Process Technologies
- Cadence Digital Full Flow Optimized to Deliver Improved Quality of Results with Up to 3X Faster Throughput
- Cadence Tools and Flows Achieve Production-Ready Certification for TSMC’s 12FFC Process
- Cadence Reference Flow with Digital and Signoff Tools Certified on Samsung’s 10nm Process Technology
Customers
Our products enable the reception of broadband data and video content, requiring high levels of performance, small silicon die-size, and rapid time to market. Innovus Implementation System has provided us with unprecedented full-flow speed-up, so we can deliver reliable designs to market faster.
Dr. Paolo Miliozzi, Senior Director, SOC Technology and Physical Design, MaxLinear
We've tested the full Innovus Implementation System flow on some of our most congestion-challenged 28nm networking IP blocks and have achieved excellent results while seeing significant throughput improvements. The new Cadence solution has enabled us to resolve our most difficult timing requirements…
Fares Bagh, Vice President, Hardware and Architecture Engineering in Freescale's Digital Networking Group
Our next system-on-chip (SoC) projects will be on a 16nm process, and the Innovus Implementation System can enable much larger blocks than previously possible, decreasing area and top-level complexity.
Debashis Basu, SVP Engineering, Silicon and Systems Engineering, Juniper Networks
Innovus Implementation System provided us with substantial gains in quality of results and speed-up for our most challenging design.
Tatsuji Kagatani, Dept. Manager, Design Automation Dept., Elemental Technology Development Division at Renesas System Design Co., Ltd.
At ARM, we push the limits of silicon and EDA tool technology to deliver products on tight schedules required for consumer markets. We partnered closely with Cadence to utilize the Innovus Implementation System during the development of our ARM® Cortex®-A72 processor. This demonstrated a 5X runtime improvement…
Noel Hurley, General Manager, CPU Group, ARM
The Innovus Implementation System significantly improved the runtime on a critical multi-million-cell IP core compared to our previous solution. With runtimes improved to deliver more than a million cells per day of implementation throughput, we can confidently drive our aggressive schedules…
Robin Lu, Vice President of ASIC, Spreadtrum Communications
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