The Cadence® Cerebrus™ Intelligent Chip Explorer is a revolutionary, machine learning-driven, automated approach to chip design flow optimization. Block engineers specify the design goals, and Cerebrus will intelligently optimize the Cadence digital full flow to meet these power, performance, and area (PPA) goals in a completely automated way. By adopting Cerebrus, it is possible for engineers to concurrently optimize the flow for multiple blocks, which is especially important for the large, complex system-on-chip (SoC) designs needed for today’s ever more powerful electronic systems. Additionally, through the Cerebrus full flow reinforcement learning technology, engineering team productivity is greatly improved.
Better PPA
Chip design flow from RTL to GDS, automatically optimized for PPA
Improved Productivity
Engineers can quickly optimize flows for many blocks concurrently and use that knowledge for the next design
Scalability
Efficient distributed compute machine learning technology, also enabled for cloud
Easy to Use
Designer cockpit allows interactive results analysis, so engineers always have control
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Machine learning-driven automated Cadence digital full flow optimization resulting in better PPA more quickly than a manual iterative approach - Optimized Cerebrus machine learning models can be the start for new projects, reducing the training effort significantly
- Cerebrus enables each designer to easily optimize the flow for multiple blocks concurrently for improved engineering productivity
- Massively distributed computing provides a scalable Cerebrus solution using on premises or cloud resources
- Sophisticated Cerebrus designer cockpit allows interactive results analysis and run management
