Cerebrus Machine Learning

The Cadence® CerebrusTM Intelligent Chip Explorer is a revolutionary, machine learning-driven, automated approach to chip design flow optimization. Block engineers specify the design goals, and Cerebrus will intelligently optimize the Cadence digital full flow to meet these power, performance, and area (PPA) goals in a completely automated way. By adopting Cerebrus, it is possible for engineers to concurrently optimize the flow for multiple blocks, which is especially important for the large, complex system-on-chip (SoC) designs needed for today’s ever more powerful electronic systems. Additionally, through the Cerebrus full flow reinforcement learning technology, engineering team productivity is greatly improved.

Key Benefits

Better PPA

Chip design flow from RTL to GDS, automatically optimized for PPA

Improved Productivity

Engineers can quickly optimize flows for many blocks concurrently and use that knowledge for the next design

Scalability

Efficient distributed compute machine learning technology, also enabled for cloud

Easy to Use

Designer cockpit allows interactive results analysis, so engineers always have control

Features

  • Machine learning-driven automated Cadence digital full flow optimization resulting in better PPA more quickly than a manual iterative approach
  • Optimized Cerebrus machine learning models can be the start for new projects, reducing the training effort significantly
  • Cerebrus enables each designer to easily optimize the flow for multiple blocks concurrently for improved engineering productivity
  • Massively distributed computing provides a scalable Cerebrus solution using on premises or cloud resources
  • Sophisticated Cerebrus designer cockpit allows interactive results analysis and run management

Videos

Machine learning-driven, automated approach to digital chip design

Using machine learning to automate chip design from RTL to GDS for full flow optimization provides PPA and Productivity...
Cerebrus Automated ML Chip Design Technology Overview

Venkat Thanvantri, VP of Machine Learning R&D, describes the innovative distributed computing and reinforcement learning...
Delivering better PPA and chip design productivity using Cerebrus Intelligent Chip...

Rod Metcalfe, ML Product Manager, explains how Cerebrus has enabled a revolution in chip design productivity, allowing...

Resources

Machine Learning-Driven Full-Flow Chip Design Automation

With the availability of massive, cloud-enabled, distributed computing and advancements in machine learning computer science, the next chip design automation revolution is now possible.

Read White paper

Cadence Extends Digital Design Leadership with ML-based Cerebrus

Cadence announced the delivery of the Cadence Cerebrus Intelligent Chip Explorer, a new ML-based tool that automates and scales digital chip design, enabling customers to efficiently achieve demanding chip design goals.

Read Press Release

Cerebrus: The Future of Intelligent Chip Design

Breakfast Byte’s blogger Paul McLellan digs into the benefits of the Cerebrus Intelligent Chip Explorer citing some results and highlighting customer feedback

Read Blog Post