Tempus Timing Solution

Aging-Aware STA

• Breakthrough technology to address aging problem for automotive, aerospace, consumer, mobile, and hyperscale designs with Liberate Characterization Solution and Tempus
• Consumes aging libraries, that supports various stress conditions and recovery, generated by Liberate Characterization Solution
• SPICE-accurate aging analysis capability for long-term reliability with better PPA
• Address instance-specific and non-uniform aging (aging context can be different than STA condition)
• Accurate analysis leading to avoiding over design and improve PPA

Tempus Power Integrity (PI)

• Breakthrough technology in providing true-signoff solution
• Seamless Tempus and Voltus integration to provide next-generation IR drop analysis and fixing technology
• Catching timing violations missed by today’s traditional IR-drop signoff methodology resulting in dead silicon
• Automated fixing by Tempus ECO the IR drop issues by optimizing both the victim and aggressor paths
• Reduce max IR-drop design margin and achieving best PPA

Timing Robustness

• Statistical measure of silicon performance
• Mathematically model design robustness using LVF libs
• Meet reliability targets (ex. 4-sigma) while significantly improving (by several %) design PPA

Silicon Prediction

• Silicon tuned continuously with quick feedback for adjusted design timing
• True signoff and optimization with predicted delays
• Better silicon with PPA improvements and timing yield prediction
• Accurate statistical modeling of identified discrete parameters of modeling silicon variations in pre-silicon signoff STA
• Performs model-to-hardware correlations to achieve silicon goodness

VT Skew Robustness

• Provides advanced techniques to address pessimistic STA methodology involving analysis of mixed VT classes
• Performs optimum permutations using PBA engine to identify worst-case slack
• Details of the VT skew robustness analysis are available in the timing report