The Cadence® Pegasus™ Design Review Environment is an easy-to-use, high performance, and standalone chip-finishing system that supports multiple formats of design, layout, and manufacturing data. The Pegasus Design Review Environment rapidly loads large layouts (GDSII, OASIS®, LEF/DEF, MEBES, and other industry- standard formats) providing a rich set of debugging and inspection features, including measurement, dynamic visualization, multiple database overlay, net connectivity tracing, cross section viewing, and GDSII/OASIS editing.
With the Pegasus Design Review Environment’s high capacity, users can load extremely large layouts in seconds. The Pegasus Design Review Environment’s signoff analysis environment allows users to place multiple layouts in one canvas and perform a range of chip-finishing functions.
The Pegasus Design Review Environment is tightly integrated with the Cadence Pegasus Verification System and offers similar use models and flows to Pegasus verification in the Cadence Innovus™ Implementation System and Cadence Virtuoso® environment in a standalone capacity. It also works with third-party implementation and verification tools. The Pegasus Design Review Environment’s high performance offers design and manufacturing teams a fast and extensible environment for efficient tapeout and chip finishing.
After full-chip verification, opening the database for chip finishing can take hours, and because there are several iterations at this stage, any productivity loss has a large impact.
Tatsuji Kagatani, Department Manager, Design Automation Department System Integration, Renesas Electronics Corporation
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