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  • Products

    • Products

      Cadence.AI

      • Millennium Platform

        AI-driven digital twin supercomputer

      • Cadence Cerebrus AI Studio

        Multi-block, multi-user SoC design platform

      • Optimality Intelligent System Explorer

        AI-driven Multiphysics analysis

      • Verisium Verification Platform

        AI-driven verification platform

      • Allegro X AI

        AI-driven PCB Design

      • Tensilica AI Platform

        On-device AI IP

    • Products

      IC Design & Verification

      • Virtuoso Studio

        Analog and custom IC design

      • Spectre Simulation

        Analog and mixed-signal SoC verification

      • Innovus+ Platform

        Synthesis and implementation for advanced nodes

      • Xcelium Logic Simulation

        IP and SoC design verification

      • Silicon Solutions

        Protocol IP and Compute IP, including Tensilica IP

      • Palladium and Protium

        Emulation and prototyping platforms

    • Products

      System Design & Analysis

      • Allegro X Design Platform

        System and PCB design platform

      • Allegro X Adv Package Designer Platform

        IC packaging design and analysis platform

      • Sigrity X Platform

        Signal and power integrity analysis platform

      • AWR Design Environment Platform

        RF and microwave development platform

      • Cadence Reality Digital Twin Platform

        Data center design and management platform

      • Fidelity CFD Platform

        Computational fluid dynamics platform

    • All Analog IC Design Products
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    • Custom Silicon Services

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    • Artificial Intelligence

    • 3D-IC Design

    • Advanced Node

    • Arm-Based Solutions

    • Chiplets

    • Cloud Solutions

    • Computational Fluid Dynamics

    • Functional Safety

    • Low Power

    • Mixed-signal

    • Molecular Simulation

    • Multiphysics System Analysis

    • Photonics

    • RF / Microwave

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    Explore Cadence Cloud Now Explore Cadence Cloud Now
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Free Trials

Pegasus Design Review Environment

Production-proven, full-chip, high-performance chip-finishing system

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Key Benefits

  • Improves full-chip signoff productivity via seamless integration with Pegasus verification, complete full-chip DRC/LVS/ERC review, job submission, and error analysis within a single cockpit
  • Fast loading, editing, and analysis of large layouts for GDSII and OASIS®
  • Easy-to use, high-performance standalone chip-finishing system, with LEF/DEF support for digital design review

Overview

The Cadence® Pegasus™ Design Review Environment is an easy-to-use, high performance, and standalone chip-finishing system that supports multiple formats of design, layout, and manufacturing data. The Pegasus Design Review Environment rapidly loads large layouts (GDSII, OASIS®, LEF/DEF, MEBES, and other industry- standard formats) providing a rich set of debugging and inspection features, including measurement,  dynamic visualization, multiple database overlay, net connectivity tracing, cross section viewing, and GDSII/OASIS editing. 

With the Pegasus Design Review Environment’s high capacity, users can load extremely large layouts in seconds. The Pegasus Design Review Environment’s signoff analysis environment allows users to place multiple layouts in one canvas and perform a range of chip-finishing functions. 

The Pegasus Design Review Environment is tightly integrated with the Cadence Pegasus Verification System and offers similar use models and flows to Pegasus verification in the Cadence Innovus™ Implementation System and Cadence Virtuoso® environment in a standalone capacity. It also works with third-party implementation and verification tools. The Pegasus Design Review Environment’s high performance offers design and manufacturing teams a fast and extensible environment for efficient tapeout and chip finishing.

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TRAINING COURSES

  • Related Products
    • Physical Verification System
    • Pegasus Layout Pattern Analyzer
    • Pegasus Computational Pattern Analytics
    • Pegasus CMP Predictor
    • Quantus Extraction Solution
    • Pegasus Verification System
News ReleasesVIEW ALL
  • Cadence and Samsung Foundry Accelerate Chip Innovation for Advanced AI and 3D-IC Applications 06/12/2024

  • Cadence and TSMC Collaborate on Wide-Ranging Innovations to Transform System and Semiconductor Design 04/24/2024

  • Cadence Signoff Solutions Empower Samsung Foundry’s Breakthrough Success on 5G Networking SoC Design 11/30/2023

  • Cadence Announces Voltus InsightAI, Industry’s First Generative AI Technology that Automatically Identifies and Addresses EM-IR Violations 11/02/2023

  • Cadence Collaborates with Arm to Accelerate Neoverse V2 Data Center Design Success with Cadence AI-driven Flows 08/30/2023

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Customers

After full-chip verification, opening the database for chip finishing can take hours, and because there are several iterations at this stage, any productivity loss has a large impact.

Tatsuji Kagatani, Department Manager, Design Automation Department System Integration, Renesas Electronics Corporation

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