Integrated Virtuoso LDE option accelerates the convergence of custom analog designs
Quantify the impact on timing and leakage of LDE on standard cell libraries
Include LDE from cell context in timing analysis and signoff to increase accuracy
The Cadence® LDE Electrical Analyzer helps designers identify, analyze, and minimize the effect of parametric issues associated with manufacturing variability to improve design performance.
LDE Electrical Analyzer is a complete and silicon-correlated electrical design-for-manufacturing (DFM) analyzer that allows you to optimize and control the impact of layout-dependent effects (LDEs), such as stress or well proximity effects (WPEs), on design performance. This tool plugs directly into your existing flows for custom analog, IP, and cell-based digital designs, helping you accelerate timing closure.
LDE Electrical Analyzer leverages the traditional foundry enablement, such as SPICE models, along with a dedicated LDE engine to extract device variability caused by LDEs. The tool integrates the LDE variability into most custom, library, and chip design flows:
Virtuoso® LDE Analyzer option: LDE Electrical Analyzer is available as an option within the Virtuoso Analog Design Environment or Virtuoso Layout Suite. Custom analog designers leverage the LDE Electrical Analyzer integrated in the Virtuoso environment for early detection of the LDE impact on design performance, device electrical properties, and device matching.
Using the LDE Electrical Analyzer’s standalone library analysis framework, standard cell library designers and users can quantify the impact on timing and leakage of LDE created by cell neighbors, and optimize characterization conditions and design margins
With LDE Electrical Analyzer, you can increase the accuracy of your timing analysis and signoff by including LDE from cell contexts
Features
Virtuoso LDE Analyzer option: For custom analog designers, the Virtuoso LDE Analyzer option in the Virtuoso ADE Product Suite and Virtuoso Layout Suite helps to accelerate design convergence, reduce the post-layout iteration, and reduce sensitivity to LDE with the following features:
LDE-Aware Simulation: Allows you to detect early on the LDE impact by creating a simulation netlist with LDE from a layout that does not need to be LVS clean or even fully placed
LDE Electrical Constraints: Enables the early detection of mismatch due to LDE, without having to complete the layout or run simulation
Layout LDE Analysis: Flags large variations in transistor electrical characteristics (idsat, Vth, etc.) between schematic assumptions and actual layout
Contribution Guidelines: For each violation reported by the layout LDE analysis, a report on the contribution of each LDE is provided to help you understand the root cause of the variation
LDE Fixing Guidelines: LDE analysis also reports actionable layout modifications, that when implemented, reduce the LDE impact on transistor electrical characteristics
Standard-cell library designers and users leverage the library LDE analysis framework to quantify, reduce, and characterize the LDE impact on standard-cell electrical performance:
Quantify variability in timing and leakage created by LDE from standard cell context
Identify and quantify source of variation to help layout optimization and reduce impact of LDE on standard-cell electrical performance
Optimize context selection for characterization; worst/best case context can be exported to Liberate™ tool or another characterization solution
Generate cell contexts and place via on pins for early printability litho checks
LDE Electrical Analyzer improves timing signoff accuracy by integrating LDE from the context on standard-cell delay in the timing analysis and signoff checks in Innovus™ Implementation System and Tempus™ Timing Signoff Solution:
Context-aware critical path analysis in designs extracts context LDE effects on critical paths. Calculates, using SPICE-level simulation, instance-derating factor for back-annotation to timing signoff engine
Cell context analysis in a design checks variability spread of critical cells, such as clock buffers using the context of the actual design, making sure it’s within margin or identifying the cells exceeding maximum variability threshold
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