Pegasus Layout Pattern Analyzer

The Cadence^® Pegasus^™ Layout Pattern Analyzer (LPA) quickly detects and automatically fixes lithography hotspots, based on either fast pattern matching and/or machine learning (ML) prediction.

Pegasus LPA detects manufacturability issues missed by traditional physical verification. Depending on the foundry enablement, the tool can either perform a pattern-based check to identify known hotspots or use a ML engine to predict unknown yield-limiting hotspots. Pegasus LPA not only provides foundry-certified fast-litho hotspot detection for signoff using pattern matching and/or ML, it also allows hotspots to be detected during implementation through tight integration with Cadence custom and digital implementation platforms. Integration with the Innovus^™ Implementation System delivers a command-line interface with the Innovus DFM option where users can seamlessly invoke Pegasus LPA in scripts and use the fixing guidelines to increase automated fixing rates. The integration of Pegasus LPA through the framework included in the Virtuoso Application Library Environment offers a friendly environment for designers to accomplish DFM tasks. Pegasus LPA is a signoff for most foundries enforcing mandatory DFM checks.

In addition to DFM checks, Pegasus LPA can perform pattern-based layout optimization (PBLO) to improve design quality, increase usage of DFM rules, and automate the fixing of complex design rules.

Key Features

• Provides fast, scalable, and foundry-certified detection of yield-limiting hotspots to meet DFM signoff requirements
• Pegasus LPA with ML technology provides greater detection efficiency with minimal runtime impact
• Produces fixing guidelines to increase automated fixing rates and minimize design change
• Integrates with current library, IP, custom analog, and cell-based digital physical design flows
• Delivers versatile pattern-based layout optimization to improve design quality