Accelerate Productivity and Time to Market with Overnight Chip-Level Signoff Closure
The Cadence Certus Closure Solution is the industry's first fully automated and massively distributed environment for full-chip optimization and signoff. It delivers up to 10X concurrent chip-level optimization and signoff. Furthermore, it supports the high-capacity requirements of modern designs with the unlimited capacity of placeable instances. It employs a new architecture based on massive parallelism to support true, fully automated, and massively distributed hierarchical optimization and signoff closure for the full chip.
Its massively distributed computing ability provides simultaneous full-chip optimization, implementation in the Innovus Implementation System, metal fill with Pegasus Physical Verification System, parasitic extraction with the Quantus Extraction Solution, and full static timing analysis with the Tempus Signoff Solution. Using scalable architecture allows a massively distributed and simultaneous optimization and signoff flow for 3D-IC designs of multi-millions-instance dies from same or different process nodes and inter-DIE paths in a tightly integrated Integrity 3D-IC solution.