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  • Products

    • Products

      Cadence.AI

      • Millennium Platform

        AI-driven digital twin supercomputer

      • Cadence Cerebrus AI Studio

        Multi-block, multi-user SoC design platform

      • Optimality Intelligent System Explorer

        AI-driven Multiphysics analysis

      • Verisium Verification Platform

        AI-driven verification platform

      • Allegro X AI

        AI-driven PCB Design

      • Tensilica AI Platform

        On-device AI IP

    • Products

      IC Design & Verification

      • Virtuoso Studio

        Analog and custom IC design

      • Spectre Simulation

        Analog and mixed-signal SoC verification

      • Innovus+ Platform

        Synthesis and implementation for advanced nodes

      • Xcelium Logic Simulation

        IP and SoC design verification

      • Silicon Solutions

        Protocol IP and Compute IP, including Tensilica IP

      • Palladium and Protium

        Emulation and prototyping platforms

    • Products

      System Design & Analysis

      • Allegro X Design Platform

        System and PCB design platform

      • Allegro X Adv Package Designer Platform

        IC packaging design and analysis platform

      • Sigrity X Platform

        Signal and power integrity analysis platform

      • AWR Design Environment Platform

        RF and microwave development platform

      • Cadence Reality Digital Twin Platform

        Data center design and management platform

      • Fidelity CFD Platform

        Computational fluid dynamics platform

    • All Analog IC Design Products
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    • Custom Silicon Services

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    • Artificial Intelligence

    • 3D-IC Design

    • Advanced Node

    • Arm-Based Solutions

    • Chiplets

    • Cloud Solutions

    • Computational Fluid Dynamics

    • Functional Safety

    • Low Power

    • Mixed-signal

    • Molecular Simulation

    • Multiphysics System Analysis

    • Photonics

    • RF / Microwave

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    Explore Cadence Cloud Now Explore Cadence Cloud Now
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Assura Physical Verification

Trusted custom/analog signoff for mature nodes

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Key Benefits

  • Trusted custom/analog signoff for mature nodes
  • Integrated with Virtuoso AMS/custom design and simulation technologies
  • Decreases overall DRC/LVS signoff iterations with an intuitive Virtuoso platform-based debug environment

Cadence® Assura® Physical Verification supports both interactive and batch operation modes with a single set of design rules. The tool uses hierarchical- and multi-processing for fast, efficient identification and correction of design rule errors. Unique pattern-checking capabilities enable simple rule development and maintenance for hard-to-write rules. Assura Physical Verification is supported where foundry rule decks are available.

 

Assura Physical Verification reduces overall verification time because it incorporates a fast and intuitive debug capability integrated within the Virtuoso® environment. It facilitates schematic-to-layout cross-probing and incorporates technologies that fix, extract, and compare errors. An interactive short locator accelerates recognition and fixing of shorts. Assura Physical Verification also offers plug-and-play integration with transistor-based Cadence Quantus™ Extraction Solution. 

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TRAINING COURSES

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    • Physical Verification System
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News ReleasesVIEW ALL
  • Cadence and Samsung Foundry Accelerate Chip Innovation for Advanced AI and 3D-IC Applications 06/12/2024

  • Cadence and TSMC Collaborate on Wide-Ranging Innovations to Transform System and Semiconductor Design 04/24/2024

  • Cadence Signoff Solutions Empower Samsung Foundry’s Breakthrough Success on 5G Networking SoC Design 11/30/2023

  • Cadence Announces Voltus InsightAI, Industry’s First Generative AI Technology that Automatically Identifies and Addresses EM-IR Violations 11/02/2023

  • Cadence Collaborates with Arm to Accelerate Neoverse V2 Data Center Design Success with Cadence AI-driven Flows 08/30/2023

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