OVERVIEW
Getting an accurate measure of RTL power consumption during design exploration has long been a major challenge for SoC design teams. System-level verification tools have the capacity to exercise real use cases, but they are disconnected from the implementation tools that translate RTL to gates and wires and from signoff tools that validate the final design.
Cadence Joules RTL Power Solution closes this gap by delivering time-based RTL power analysis with system-level runtimes and capacity while still providing high-quality estimates of gates and wires.
KEY BENEFITS
RTL power estimates within 15% of signoff, including glitch power from RTL stimulus
Up to 20X faster time-based power analysis, with unique ideal power-guided RTL power reduction methodology
Direct integration with Palladium and Xcelium platforms for power analysis of workloads, identifying critical windows of interest
Native integration inside Innovus, Genus, and Stratus HLS technologies for automatic power optimization
FEATURES
RESOURCES
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