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Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.

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  • Products
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Genus Synthesis Solution
          • Conformal Smart LEC
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Virtuoso RF Solution
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus IC Power Integrity Solution
          • RESOURCES
          • Flows
      • Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Emulation and Prototyping
          • Formal and Static Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • JasperGold Formal Verification Platform
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
      • IP
        • PRODUCT CATEGORIES
          • Interface IP
          • Denali Memory IP
          • Tensilica Processor IP
          • Analog IP
          • System / Peripherals IP
          • Verification IP
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
      • System Analysis
        • PRODUCT CATEGORIES
          • Computational Fluid Dynamics
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Signal and Power Integrity
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Omnis
          • Sigrity Advanced SI
          • Sigrity Advanced PI
          • RESOURCES
          • System Analysis Resources Hub
          • AWR Free Trial
      • Embedded Software
      • PCB Design and Analysis
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • RESOURCES
          • What's New in Allegro
          • What's New in Sigrity
          • Advanced PCB Design & Analysis Resources Hub
          • Flows
    • PERVASIVE INTELLIGENCE
      • AI / Machine Learning
      • AI IP Portfolio
    • CADENCE CLOUD
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        • Cloud Solutions
        • Low Power
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        • AI / Machine Learning
      • Technologies
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Conformal Smart LEC

Massively parallel adaptive-proof architecture improves runtime by an average of 4X

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Key Benefits

  • Average of 4X runtime improvement with the same compute resources over existing solution
  • Adaptive-proof technology eliminates manual iterations of verification strategies
  • Massively parallel, scalable architecture supports distributed processing delivering potentially over 20X runtime improvement

With rapidly growing chip functionality, design sizes are increasing. In addition, with the latest advances in logic synthesis at advanced nodes, designers make aggressive pushes in synthesis to achieve power, performance, and area (PPA) goals. These advances in both design size and complexity stress today’s equivalence checking proof methods and can result in long RTL-to-gate runtimes and, sometimes, inconclusive results. Equivalence checking is a critical step in digital tapeout flows, and the Conformal Smart Logic Equivalence Checker (LEC) solution addresses these issues.

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Key Features

Massively parallel architecture automatically partitions designs, distributes formal proof strategies across multiple machines and CPUs, and can scale seamlessly to 100s of CPUs for improved runtime. This process is fully transparent to the user and does not require manual configuration.

Adaptive-proof technology finds the fastest solution to a conclusive proof with minimal user effort. It analyzes each partition and determines the optimal formal algorithm to minimize runtime and avoid proof timeouts—especially on designs with complex behavioral datapath components.

With the adaptive-proof technology and scalable, massively parallel architecture, designers can potentially improve their runtime by more than 20X.

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TRAINING COURSES

See how you can achieve dramatic runtime improvement for logic equivalence checks

  • Related Products

    • Conformal Equivalence Checker
    • Genus Synthesis Solution
    • Innovus Implementation System
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  • Cadence Delivers Automotive Reference Flow for Samsung Foundry 14LPU Process Technology 04/08/2021

  • Cadence Unveils Next-Generation Palladium Z2 and Protium X2 Systems to Dramatically Accelerate Pre Silicon Hardware Debug and Software Validation 04/05/2021

  • Cadence Successfully Tapes Out Tensilica SoC on GLOBALFOUNDRIES 22FDX Platform Using Adaptive Body Bias Feature 03/24/2021

  • GLOBALFOUNDRIES and Cadence Add Machine Learning Capabilities to DFM Signoff for GF’s Most Advanced FinFET Solutions 03/23/2021

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