As technology advances, both manufacturing and design complexity grow. Designs are being scaled down to meet the ever-increasing demand for more functionality contained in a single chip, creating unique implementation challenges. Manufacturing is facing huge challenges in terms of printability, manufacturability, yield ramp-up, and variability. Unfortunately, restrictions on power, performance, and area (PPA) or turnaround time (TAT) do not scale up along with these factors.
To addresses these challenges, physical verification and implementation solutions have been augmented with in-design and signoff design for manufacturing (DFM) checks and automated DFM enhancement so designers can reduce the impact of variability and improve the manufacturability of their designs. Foundries need high-capacity, accurate modeling and efficient design analysis, yield enhancements, and mask data preparation in their fab.
Cadence® DFM solutions address both designer and manufacturer challenges, including lithography, chemical and mechanical polishing (CMP), layout-dependent effects (LDE), layout and yield analysis, and optical proximity correction (OPC). This complete suite of manufacturability and variability solutions is used by both designers and manufacturers to improve design manufacturability and reduce the time to yield.
Cadence DFM solutions comprise:
Litho Physical Analyzer (LPA)
Improves your systematic and parametric yield and meets foundry DFM signoff requirements. Detects and corrects lithography hotspots, based on either fast, accurate silicon contour prediction or high-performance pattern matching. LPA is also integrated into Innovus™ and Virtuoso™ implementation platforms to deliver in-design detection and automated fixing with fast turnaround time, improved fixing rate using LPA fixing guidelines, and ease-of-use though seamless integration. LPA is qualified by all major foundries.
Layout Dependant Effects (LDE) Electrical Analyzer
Allows designers to identify, analyze, and minimize the effect of parametric issues associated with manufacturing variability to improve chip performance.
Cadence CMP Predictor (CCP)
Enhances design performance and yield through model-based entire-stack thickness prediction, CMP hotspot detection, and CMP-aware RC extraction. CCP is qualified by all major foundries.
Process and Proximity Compensation (PPC)
A complete and comprehensive third-generation mask pattern synthesis solution built from the ground up for correct-by-construction OPC with the fastest mask cycle time.
Cadence Pattern Analysis (CPA)
A versatile layout processing tool suite with unmatched performance. Its high-capacity, high-performance layout analysis and optimization for design and manufacturing teams is used to improve manufacturability and reduce time to yield.