Cadence Conformal Technologies

Providing formal verification technology for fast, accurate bug detection and correction

Cadence Conformal Equivalence Checker (EC) makes it possible to verify and debug multi-million–gate designs without using test vectors. It offers the industry’s only complete equivalence checking solution for verifying SoC designs—from RTL to final LVS netlist (SPICE). Cadence Conformal EC enables designers to verify the widest variety of circuits, including complex arithmetic logic, datapaths, memories, and custom logic.

Key Benefits:

• Exhaustively verifies multi-million-gate ASICs several times faster than traditional gate-level simulation
• Decreases the risk of missing critical bugs with independent verification technology
• Enables faster, more accurate bug detection and correction throughout the entire design flow
• Extends equivalence checking capability to complex datapaths and closes the RTL-to-layout verification gap (XL configuration)
• Ensures RTL models perform the same functions as the corresponding transistor circuits implemented on silicon (GXL configuration)

Delivers ECO automation for greater predictability and design convergence

Cadence Conformal ECO Designer enables you to implement RTL engineering change orders (ECOs) for pre- and post-mask layout, and offers early ECO prototyping capabilities for driving critical yes/no project decisions.

ECOs have a wide variety of implementations ranging from adding or removing logic in a design to more subtle changes, such as cleaning up routing for signal integrity. All ECOs are focused on delivering products to market as fast as possible with minimal risk to correctness and schedule. ECOs can be a time of high stress, long work hours, and uncertainty. Even if the logic change is implemented in the netlist, there might not be enough spare gates on the mask to implement the change.

Key Benefits:

• Provides faster turnaround time by minimizing manual intervention and eliminating time-consuming iterations
• Generates early estimates on ECO feasibility by quantifying designer intent
• Implements complex ECOs that are typically not attempted manually

Enables the creation and validation of power intent in the context of a design

Conformal technology combines low-power equivalence checking with structural and functional checks to enable full-chip verification of power-efficient designs.

Optimizing designs for leakage and dynamic power helps designers reduce energy consumption and packaging costs. These advanced low-power design methods can also complicate the verification task, introducing risk during synthesis and physical implementation.

Full-chip, gate-level simulation is not a practical or scalable methodology for verifying today’s large, complex designs. Conformal low power enables designers to create power intent and verify and debug multi-million-gate designs without simulating test vectors. It combines low-power structural and functional checks with world-class equivalence checking to provide superior performance, capacity, and ease of use.

Key Benefits:

• Reduces the risk of silicon re-spins by providing complete verification coverage
• Detects low-power implementation errors early in the design cycle
• Verifies multi-million-gate designs much faster than traditional gate-level simulation
• Closes the RTL-to-layout verification gap using low-power equivalence checking
• Decreases the risk of missing critical bugs through independent verification technology
• Enables power intent creation and integration without having to become a power format expert

Delivers the fastest path to full-chip constraints and CDC signoff

Achieving first-pass silicon success with rapid execution is a growing challenge for today’s complex designs. Structural signoff is an important step to achieving this success. Converging on signoff-quality constraints to meet aggressive power, performance, and area (PPA) requirements and signing off on clock domain crossings (CDCs) with accurate constraints are critical in this process.

Cadence Conformal Litmus is the next-generation tool that delivers the fastest path to SoC-level constraints signoff and CDC signoff.

Key Benefits:

• The industry’s first static timer integration for constraints and CDC signoff enables modeling the design and constraints, using the same interpretation as the Tempus Timing Signoff Solution, to provide customers with 100% signoff accuracy at the RTL
• CDC signoff verifies the structural correctness of CDC in the design from early RTL through implementation
• Constraints signoff checks for correctness and completeness of constraints at the IP level and lets users perform hierarchical block versus top consistency checks at the SoC integration level
• Smart analysis generates accurate low-noise reports, providing insights into the design and the constraints intent and enabling users to diagnose root cause failures and signoff rapidly, thereby saving weeks to months in the design schedule
• Multi-CPU parallelization delivers up to 10X faster turnaround time on SoC designs

Delivers automated validation and refinement of timing constraints from RTL to layout

Cadence Conformal Constraint Designer provides a complete and efficient path to develop and manage constraints and clock-domain crossings (CDCs), ensuring they are functionally correct from RTL to layout. By pinpointing real design issues quickly and accurately, delivering higher quality timing constraints, and finding issues with clock-domain synchronizers, the solution helps you reduce overall design cycle times and enhance the quality of silicon in complex SoC designs.

With Conformal Constraint Designer, you can reduce the risk of respins through formal validation of constraints. Since the solution quickly validates failing timing paths as functionally false, it speeds convergence for timing closure. It also creates initial constraints effortlessly with the SDC advisor.

Key Benefits:

• Ensures timing constraints are correct and complete
• Shortens design cycles with a comprehensive analysis environment that checks the creation and integration of block-level and top-level constraints
• Validates that CDCs have proper synchronizers in place, easily visualized through a FIFO manager