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  • Products

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      Cadence.AI

      • Millennium Platform

        AI-driven digital twin supercomputer

      • Cadence Cerebrus AI Studio

        Multi-block, multi-user SoC design platform

      • Optimality Intelligent System Explorer

        AI-driven Multiphysics analysis

      • Verisium Verification Platform

        AI-driven verification platform

      • Allegro X AI

        AI-driven PCB Design

      • Tensilica AI Platform

        On-device AI IP

    • Products

      IC Design & Verification

      • Virtuoso Studio

        Analog and custom IC design

      • Spectre Simulation

        Analog and mixed-signal SoC verification

      • Innovus+ Platform

        Synthesis and implementation for advanced nodes

      • Xcelium Logic Simulation

        IP and SoC design verification

      • Silicon Solutions

        Protocol IP and Compute IP, including Tensilica IP

      • Palladium and Protium

        Emulation and prototyping platforms

    • Products

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      • Allegro X Design Platform

        System and PCB design platform

      • Allegro X Adv Package Designer Platform

        IC packaging design and analysis platform

      • Sigrity X Platform

        Signal and power integrity analysis platform

      • AWR Design Environment Platform

        RF and microwave development platform

      • Cadence Reality Digital Twin Platform

        Data center design and management platform

      • Fidelity CFD Platform

        Computational fluid dynamics platform

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Liberate Variety Statistical Characterization

Fast, accurate process variation characterization

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Key Benefits

  • Creates variation-aware timing models that account for both systemic process variations and random process variations
  • Includes tool libraries for modeling both local and global variations
  • Enables SSTA or conventional static timing analysis

 

The Cadence® Liberate™ Variety™ statistical characterization solution provides an ultra-fast standard cell characterization of process-variation-aware timing models. Liberate Variety characterization generates libraries that can be used with multiple SSTAs without requiring re-characterization for each unique format. Variety characterization also generates AOCV and SOCV tables and LVF.

Features
  • Creates variation-aware timing models that account for both systematic process variations (e.g., variations due to lithography) and random process variations for any set of correlated or uncorrelated process parameters (e.g., variations due to doping fluctuations between transistors)
  • Tool libraries can be used to model both local (within cell and within die) variations and global die-to-die variations
  • Enables SSTA or conventional static timing analysis with on-chip variation tables to provide a more realistic estimation of timing relative to actual silicon performance, which often reduces worst-case timing margins by 10-15%, resulting in a higher yielding design that can be taped out sooner

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TRAINING COURSES

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    • [REDIRECT] Spectre Accelerated Parallel Simulator
    • Liberate LV Library Validation Solution
    • Liberate Variety Statistical Characterization
    • [REDIRECT] Liberate Characterization Solution
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    • [REDIRECT] Spectre eXtensive Partitioning Simulator (XPS)
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Invecas Offers EM-Based Max Capacitance Limits for Standard Cells with Liberate Characterization

Ultra-Low Voltage SRAM: Addressing the Characterization Challenge

Getting What You’re Entitled to at 10nm by Reducing Timing Pessimism

Characterizing 22FDX Library at GLOBALFOUNDRIES

Accurate and Faster SoC Signoff with Simulation-Based AMS Characterization

Liberate MX Product Demonstration

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