Key Benefits
- Creates variation-aware timing models that account for both systemic and random process variations
- Local and global process variation
- Generates AOCV/SOCV tables and LVF
The Cadence® Liberate™ Trio Characterization Suite provides an ultra-fast standard-cell characterizer of process variation-aware timing models. It can generate libraries that can be used with multiple SSTAs without requiring re-characterization for each unique format. The Liberate Trio suite can generate advanced on-chip variation (AOCV) tables, statistical on-chip variation (SOCV) tables, and Liberty Variation Format (LVF)
It can also calculate non-linear sensitivity, accounting for systematic and random variation for any set of correlated or uncorrelated process parameters. The resulting libraries can be used to model both local (within-cell and within-die) variations and global die-to-die variations.
This features is also offered as a standalone option.
Press Releases (5)
- Cadence Achieves EDA Certification for TSMC 5nm and 7nm+ FinFET Process Technologies to Facilitate Mobile and HPC Design Creation | Cadence
- Cadence Collaborates with TSMC to Advance 5nm and 7nm+ Mobile and HPC Design Innovation | Cadence
- Cadence Achieves TÜV SÜD’s First Comprehensive “Fit for Purpose - TCL1” Certification in Support of Automotive ISO 26262 Standard | Cadence
- Cadence Tools and Flows Achieve Production-Ready Certification for TSMC’s 12FFC Process | Cadence
- Cadence Custom/Analog and Full-Flow Digital and Signoff Tools Enabled for GLOBALFOUNDRIES 7LP Process Node | Cadence
Video (5)
- Invecas Provides Electromigration-Based Maximum Capacitance Limits for Standard Cell Library Using Cadence Virtuoso Liberate Characterization Solution
- Characterizing 22FDX Library at GLOBALFOUNDRIES
- Faster Timing Characterization of Analog Macros
- Accurate and Faster SoC Signoff with Simulation-Based AMS Characterization
- Statistical Characterization Approach Using Liberate MX with 40nm Low Voltage SRAM
