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Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.

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Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.

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  • Products
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Genus Synthesis Solution
          • Conformal Smart LEC
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Virtuoso RF Solution
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus IC Power Integrity Solution
          • RESOURCES
          • Flows
      • System Design and Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Emulation
          • Formal and Static Verification
          • FPGA-Based Prototyping
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • JasperGold Formal Verification Platform
          • Xcelium Logic Simulation
          • Palladium Z1 Enterprise Emulation Platform
          • Protium X1 Enterprise Prototyping Platform
          • System VIP
          • RESOURCES
          • Flows
      • IP
        • PRODUCT CATEGORIES
          • Interface IP
          • Denali Memory IP
          • Tensilica Processor IP
          • Analog IP
          • System / Peripherals IP
          • Verification IP
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
      • System Analysis
        • PRODUCT CATEGORIES
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Sigrity Advanced SI
          • Sigrity Advanced PI
          • RESOURCES
          • System Analysis Resources Hub
      • Embedded Software
      • PCB Design and Analysis
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • RESOURCES
          • What's New in Allegro
          • What's New in Sigrity
          • Advanced PCB Design & Analysis Resources Hub
          • Flows
    • PERVASIVE INTELLIGENCE
      • AI / Machine Learning
      • AI IP Portfolio
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        • Cloud Solutions
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
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        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • AI / Machine Learning
      • Technologies
        • 3D-IC Design
        • Advanced Node
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        • Low Power
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Liberate MX Memory Characterization

Fast and accurate memory characterization

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Key Benefits

  • Characterizes large macro blocks efficiently and accurately
  • Delivers fast runtime
  • Performs independently accurate SPICE characterization runs
  • TÜV SÜD “Fit for Purpose – TCL1” certified to meet ISO 26262 automotive functional safety requirements
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The Cadence® Liberate™ MX memory characterization solution extends Cadence’s ultra-fast standard cell and I/O library characterization capabilities to cover larger macro blocks such as memory and custom cores. Macro blocks require additional pre-analysis steps in order to make fast and accurate characterization feasible. The Liberate MX solution leverages a network of distributed CPUs and utilizes the patented Inside View technology for optimizing characterization runtime. In this way, memories and cores can be characterized quickly and easily with the same accuracy and methods as standard cells, including the generation of timing constraints and modeling of current source models for timing and noise.

Automotive TCL1 Certified for ISO 26262

The industry’s first digital implementation and signoff flow to achieve “Fit for Purpose - Tool Confidence Level 1 (TCL1)” certification enables you to meet stringent ISO 26262 automotive safety requirements. The Liberate Characterization Solution is part of the flow covering RTL-to-GDSII implementation and signoff. For information on the safety manuals, Tool Confidence Analysis (TCA) documents, and compliance reports from TÜV SÜD, download the Functional Safety Documentation Kits through Cadence Online Support.

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TRAINING COURSES

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    • Liberate Trio Characterization Suite
    • Liberate AMS Mixed-Signal Characterization
    • Liberate Variety Statistical Characterization
  • Related Info

    • Cadence and Texas Instruments Success Story
    • Addressing Process Variation and Reducing Timing Pessimism at 16nm and Below White Paper
Videos

Invecas Provides Electromigration-Based Maximum Capacitance Limits for Standard Cell Library Using Cadence Virtuoso Liberate Characterization Solution

Getting What You’re Entitled to at 10nm by Reducing Timing Pessimism

Characterizing 22FDX Library at GLOBALFOUNDRIES

Liberate MX Product Demonstration

Accurate and Faster SoC Signoff with Simulation-Based AMS Characterization

Statistical Characterization Approach Using Liberate MX with 40nm Low Voltage SRAM

News ReleasesVIEW ALL
  • Cadence Achieves EDA Certification for TSMC 5nm and 7nm+ FinFET Process Technologies to Facilitate Mobile and HPC Design Creation 10/01/2018

  • Cadence Launches Liberate Trio Characterization Suite Employing Machine Learning and Cloud Optimizations 06/25/2018

  • Cadence Collaborates with TSMC to Advance 5nm and 7nm+ Mobile and HPC Design Innovation 05/01/2018

  • Cadence Achieves TÜV SÜD’s First Comprehensive “Fit for Purpose - TCL1” Certification in Support of Automotive ISO 26262 Standard 10/11/2017

  • Cadence Tools and Flows Achieve Production-Ready Certification for TSMC’s 12FFC Process 09/11/2017

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