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  • Products
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Integrity 3D-IC Platform
          • Cadence Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Voltus IC Power Integrity Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Spectre FX Simulator
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus-Fi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Virtual Prototyping
          • Emulation and Prototyping
          • Static and Formal Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
      • IP
        • PRODUCT CATEGORIES
          • 112G/56G SerDes
          • Chiplet and D2D
          • Denali Memory Interface and Storage IP
          • Interface IP
          • PCIe and CXL
          • Tensilica Processor IP
        • RESOURCES
          • Discover PCIe
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
      • Multiphysics System Analysis
        • PRODUCT CATEGORIES
          • Computational Fluid Dynamics
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Signal and Power Integrity
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Solver Cloud
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Fidelity CFD
          • Sigrity Advanced SI
          • Celsius Advanced PTI
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          • System Analysis Center
          • System Analysis Resources Hub
          • AWR Free Trial
      • Embedded Software
      • PCB Design and Analysis
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • Allegro X Design Platform
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Liberate LV Library Validation Solution

Validate a complete library overnight

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Key Benefits

  • Enables ultra-fast throughput to complete library validation overnight on a small number of multi-core computers
  • For library providers, assures the library quality before the library is shipped
  • For library users, allows cross-checking of the incoming library and provides a clear understanding of the impact of any changes due to revisions of extracted cell netlists or process models
  • Ensures coverage of all function descriptions, necessary timing, noise, power, leakage arcs, and states in the input library directly against the transistor-level circuit
  • TÜV SÜD “Fit for Purpose – TCL1” certified to meet ISO 26262 automotive functional safety requirements
ASK US A QUESTION

 

The Cadence® Liberate™ LV library validation solution provides a comprehensive library validation system including function equivalence and data consistency checking, revision analysis, and correlation with various electrical analysis tools for timing, noise, and power.

The Liberate LV solution provides a collection of utilities for validating libraries, including functional equivalence checking, data consistency checking, revision analysis, and correlation with various electrical analysis tools for timing, noise, and power. The Liberate LV solution provides the means to validate and verify the final library to ensure consistency, completeness, and accuracy.

Automotive TCL1 Certified for ISO 26262

The industry’s first digital implementation and signoff flow to achieve “Fit for Purpose - Tool Confidence Level 1 (TCL1)” certification enables you to meet stringent ISO 26262 automotive safety requirements. The Liberate Characterization Solution is part of the flow covering RTL-to-GDSII implementation and signoff. For information on the safety manuals, Tool Confidence Analysis (TCA) documents, and compliance reports from TÜV SÜD, download the Functional Safety Documentation Kits through Cadence Online Support.

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TRAINING COURSES

  • Related Products

    • Liberate LV Library Validation Solution
    • Liberate MX Memory Characterization
    • Liberate AMS Mixed-Signal Characterization
    • Liberate Characterization Solution
    • Liberate Variety Statistical Characterization
    • Spectre Accelerated Parallel Simulator
Resource Library

Press Releases (10)

  • Cadence Collaborates with TSMC to Advance 5nm and 7nm+ Mobile and HPC Design Innovation
  • Cadence Achieves TÜV SÜD’s First Comprehensive “Fit for Purpose - TCL1” Certification in Support of Automotive ISO 26262 Standard
  • Cadence Tools and Flows Achieve Production-Ready Certification for TSMC’s 12FFC Process
  • Cadence Custom/Analog and Full-Flow Digital and Signoff Tools Enabled for GLOBALFOUNDRIES 7LP Process Node
  • Cadence and TSMC Advance 7nm FinFET Designs for Mobile and HPC Platforms
  • Cadence Design Tools Certified for TSMC 7nm Design Starts and 10nm Production
  • Cadence and Intel Collaborate to Release 14nm Library Characterization Reference Flow for Customers of Intel Custom Foundry
  • TSMC Adopts Cadence Solutions for 16nm FinFET Library Characterization
  • ARM Implements the Cadence Library Characterization Solution for Advanced Node Foundation IP Development
  • Cadence Characterization Solution for Complex Multi-bit Cells Delivers Power and Performance Benefits for Yamaha

Success Story Video (3)

  • Invecas Provides Electromigration-Based Maximum Capacitance Limits for Standard Cell Library Using Cadence Virtuoso Liberate Characterization Solution
  • Characterizing 22FDX Library at GLOBALFOUNDRIES
  • Faster Timing Characterization of Analog Macros

Presentation (1)

  • Ultra-Low Voltage SRAM: Addressing the Characterization Challenge

Video (8)

  • Invecas Provides Electromigration-Based Maximum Capacitance Limits for Standard Cell Library Using Cadence Virtuoso Liberate Characterization Solution
  • Ultra-Low Voltage SRAM: Addressing the Characterization Challenge
  • Characterizing 22FDX Library at GLOBALFOUNDRIES
  • Getting What You’re Entitled to at 10nm by Reducing Timing Pessimism
  • Faster Timing Characterization of Analog Macros
  • Accurate and Faster SoC Signoff with Simulation-Based AMS Characterization
  • Liberate MX Product Demonstration
  • Statistical Characterization Approach Using Liberate MX with 40nm Low Voltage SRAM

Datasheet (1)

  • Liberate Characterization Portfolio Datasheet
VIEW ALL
Videos

Getting What You’re Entitled to at 10nm by Reducing Timing Pessimism

Characterizing 22FDX Library at GLOBALFOUNDRIES

Faster Timing Characterization of Analog Macros

Liberate MX Product Demonstration

Accurate and Faster SoC Signoff with Simulation-Based AMS Characterization

Statistical Characterization Approach Using Liberate MX with 40nm Low Voltage SRAM

News ReleasesVIEW ALL
  • Cadence Collaborates with TSMC to Advance 5nm and 7nm+ Mobile and HPC Design Innovation 05/01/2018

  • Cadence Achieves TÜV SÜD’s First Comprehensive “Fit for Purpose - TCL1” Certification in Support of Automotive ISO 26262 Standard 10/11/2017

  • Cadence Tools and Flows Achieve Production-Ready Certification for TSMC’s 12FFC Process 09/11/2017

  • Cadence Custom/Analog and Full-Flow Digital and Signoff Tools Enabled for GLOBALFOUNDRIES 7LP Process Node 06/20/2017

  • Cadence and TSMC Advance 7nm FinFET Designs for Mobile and HPC Platforms 09/22/2016

Blogs VIEW ALL
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