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  • Products

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      Cadence.AI

      • Millennium Platform

        AI-driven digital twin supercomputer

      • Cadence Cerebrus AI Studio

        Multi-block, multi-user SoC design platform

      • Optimality Intelligent System Explorer

        AI-driven Multiphysics analysis

      • Verisium Verification Platform

        AI-driven verification platform

      • Allegro X AI

        AI-driven PCB Design

      • Tensilica AI Platform

        On-device AI IP

    • Products

      IC Design & Verification

      • Virtuoso Studio

        Analog and custom IC design

      • Spectre Simulation

        Analog and mixed-signal SoC verification

      • Innovus+ Platform

        Synthesis and implementation for advanced nodes

      • Xcelium Logic Simulation

        IP and SoC design verification

      • Silicon Solutions

        Protocol IP and Compute IP, including Tensilica IP

      • Palladium and Protium

        Emulation and prototyping platforms

    • Products

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      • Allegro X Design Platform

        System and PCB design platform

      • Allegro X Adv Package Designer Platform

        IC packaging design and analysis platform

      • Sigrity X Platform

        Signal and power integrity analysis platform

      • AWR Design Environment Platform

        RF and microwave development platform

      • Cadence Reality Digital Twin Platform

        Data center design and management platform

      • Fidelity CFD Platform

        Computational fluid dynamics platform

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    • Computational Fluid Dynamics

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Liberate LV Library Validation Solution

Validate a complete library overnight

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Key Benefits

  • Enables ultra-fast throughput to complete library validation overnight on a small number of multi-core computers
  • For library providers, assures the library quality before the library is shipped
  • For library users, allows cross-checking of the incoming library and provides a clear understanding of the impact of any changes due to revisions of extracted cell netlists or process models
  • Ensures coverage of all function descriptions, necessary timing, noise, power, leakage arcs, and states in the input library directly against the transistor-level circuit
  • TÜV SÜD “Fit for Purpose – TCL1” certified to meet ISO 26262 automotive functional safety requirements

 

The Cadence® Liberate™ LV library validation solution provides a comprehensive library validation system including function equivalence and data consistency checking, revision analysis, and correlation with various electrical analysis tools for timing, noise, and power.

The Liberate LV solution provides a collection of utilities for validating libraries, including functional equivalence checking, data consistency checking, revision analysis, and correlation with various electrical analysis tools for timing, noise, and power. The Liberate LV solution provides the means to validate and verify the final library to ensure consistency, completeness, and accuracy.

Automotive TCL1 Certified for ISO 26262

The industry’s first digital implementation and signoff flow to achieve “Fit for Purpose - Tool Confidence Level 1 (TCL1)” certification enables you to meet stringent ISO 26262 automotive safety requirements. The Liberate Characterization Solution is part of the flow covering RTL-to-GDSII implementation and signoff. For information on the safety manuals, Tool Confidence Analysis (TCA) documents, and compliance reports from TÜV SÜD, download the Functional Safety Documentation Kits through Cadence Online Support.

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TRAINING COURSES

  • Related Products
    • Liberate LV Library Validation Solution
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    • Liberate AMS Mixed-Signal Characterization
    • [REDIRECT] Liberate Characterization Solution
    • Liberate Variety Statistical Characterization
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Resource Library
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  • Invecas Offers EM-Based Max Capacitance Limits for Standard Cells with Liberate Characterization
  • Getting What You’re Entitled to at 10nm by Reducing Timing Pessimism
    • Invecas Offers EM-Based Max Capacitance Limits for Standard Cells with Liberate Characterization
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