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Digital Design and Signoff

Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.

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Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.

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Verification

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Embedded Software

PCB Design and Analysis

Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.

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  • Products
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
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          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
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          • Integrity 3D-IC Platform
          • Cadence Cerebrus Intelligent Chip Explorer
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          • Spectre X Simulator
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          • RESOURCES
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          • Debug Analysis
          • Virtual Prototyping
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          • Verification IP
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        • FEATURED PRODUCTS
          • vManager Verification Management
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
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          • System VIP
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      • IP
        • PRODUCT CATEGORIES
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          • Chiplet and D2D
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          • PCIe and CXL
          • Tensilica Processor IP
        • RESOURCES
          • Discover PCIe
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
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Virtuoso Layout Suite

Accelerated full custom IC layout

Read GXL Datasheet Read XL Datasheet
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Key Benefits

  • Supports custom analog, digital, and mixed-signal designs at the device, cell, block, and chip levels
  • Accelerated performance and productivity from advanced full custom polygon editing through more flexible schematic and constraint-driven assisted full custom layout, to full custom layout automation
  • Enables creation of differentiated custom silicon that is both fast and silicon accurate

As the full custom IC layout suite of the industry-leading Cadence® Virtuoso® platform, the Virtuoso Layout Suite supports custom analog, digital, and mixed-signal designs at the device, cell, block, and chip levels. The enhanced Virtuoso Layout Suite offers accelerated performance and productivity from advanced full custom polygon editing (L) through more flexible schematic-driven and constraint-driven assisted full custom layout (XL), to full custom layout automation (GXL). Seamlessly integrated with the Virtuoso Schematic Editor and the Virtuoso Analog Design Environment, the Virtuoso Layout Suite enables the creation of differentiated custom silicon that is both fast and silicon accurate.

The Virtuoso platform is the industry’s most silicon-proven, comprehensive, custom IC design platform, trusted in taping out thousands of designs each year for more than 25 years.

  • Virtuoso Layout Suite L Datasheet
  • Virtuoso Layout Suite XL Datasheet
  • Virtuoso Layout Suite GXL Datasheet

Features

  • New patented Virtuoso Layout Suite L graphics-rendering engine provides from 10X to 100X accelerated zoom, fit, pan, drag, and redraw performance on large layouts
  • New Virtuoso Layout Suite XL connectivity extractor technology accelerates trace net, probe net, and mark net performance from 10X to 50X on large layouts
  • Patented multi-user Express PCell capability continues to boost design opening performance from 10X to 20X whenever users require PCell evaluation
  • New patented stream-in engine provides accelerated performance from 2X to 20X
  • Virtuoso Layout Suite GXL Space-Based Routing technology automatically enforces process and design rules during interactive and assisted wire and bus editing
  • Virtuoso Layout Suite GXL ModGens (module generators) add a new interactive pattern-manipulation flow, making real-time customization of a high-precision structured layout very visual and simple
  • Virtuoso Layout Suite GXL Space-Based Routing technology at chip levels can deliver high-quality constraint-driven specialty routing to close thousands of nets in minutes, and new structured device-level routing capabilities that can enhance routing productivity by as much as 50%
  • The Virtuoso platform is backed by the largest number of process design kits (PDKs) available from the world’s leading foundries, for process nodes everywhere from mature 0.6µm to advanced 7nm process nodes
Image showing layout pane of Virtuoso Layout Suite XL
Vituoso Layout Suite XL

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TRAINING COURSES

  • Related Products

    • Virtuoso Schematic Editor
    • Virtuoso ADE Product Suite
    • Custom/Analog Advanced Node
    • Virtuoso Layout Suite EAD
    • Virtuoso Space-Based Router
    • Silicon Signoff and Verification
    • Virtuoso Digital Implementation
Resource Library

Video (43)

  • Samsung Foundry AMS Design Reference Flow - Advanced Node
  • Lightelligence Powers the Next Generation of Innovations Using Integrity 3D-IC Platform
  • Sequans Designs its Future 5G IoT Platform Using Virtuoso RF Solution
  • Application of Virtuoso CurvyCore Technology in the Development of Photonic Elements for a Foundry Process Design Kit (PDK)
  • Current Data-Driven Analog Routing Using Virtuoso SDR
  • On the Silicon Photonics Physical Design’s Productivity and Reliability Enhancement
  • Useful Utilities and Helpful Hacks
  • Dragon Unleashed: Voice to Virtuoso Environment
  • Samsung 3nm Cadence AMS Design Reference Flow
  • CLE Layout Development Methodologies to Enhance Productivity of Full Custom I/O and Test-Chip Design
  • CadenceTECHTALK: Maximizing Custom Layout Productivity even as the Circuit Changes
  • Design Intent Brings Efficient Communication in Analog Design
  • On-Time 5G RFICs with Fast EM Simulation and Integrated Design Flow
  • Analog Layout Automation Flow Aimed to Improve Process Porting Efficiency with Virtuoso ModGen Framework
  • From The Best Usage Of Advanced Virtuoso Functionalities
  • Technology Update: Virtuoso Design Platform 20.1 Update
  • Advanced Layout Implementation Utilizing Analog APR Flow
  • Enhancing Design Productivity by Managing RV and Parasitic Data in Real Time During Layout Implementation
  • Increase Layout Productivity Through Accurate Area Estimation for Schematic Hierarchy
  • Automated VDR Tagging and Verification Flow for Advanced Node Design
  • Improve Device Matching with Assisted Component P&R
  • How Row-Based Methodology Improves Custom Layout
  • Using Row-Based Methodology to Improve Advanced-Node Custom Layout
  • Minimize Layout Iterations and ​ EM Errors with Simulation-Driven Routing
  • Advanced Methodologies to Accelerate Your Custom Layout
  • Webinar: Improving Custom Layout with Advanced Design Methodologies - Session Two
  • Webinar: Improving Custom Layout with Advanced Design Methodologies - Session One
  • Remove Custom Layout Bottlenecks with Concurrent Editing
  • Virtuoso Design Platform for Next-Generation Custom IC and System Design
  • Toshiba Electronic Device Solutions Overcomes Complexities of Advanced-Node Designs
  • Meeting the Challenges of Chip Design Using the Virtuoso Suite
  • New Virtuoso Design Platform for Next-Generation Custom IC and System Design
  • STMicroelectronics - Improving Productivity with Virtuoso SPD
  • ams Reduces IC Development Effort by Collaborating with Cadence on Layout Productivity
  • Cadence Pattern Matching and DFM Signoff
  • Celebrating 25 Years of Virtuoso Innovation
  • Fairchild Semiconductor Eases Floorplanning Challenges of Mixed-Signal Design with Virtuoso Platform
  • Cadence In-Design DFM-LDE Adoption in ST SmartPower PDK
  • Using VSR for Chip Routing on ST smARTpower Technologies
  • Place-and-Route in Under a Day for Allegro Microsystems
  • Analog Devices Raises Productivity with ModGen Tools
  • Freescale Accelerates Layout Via Constraint-Driven Design Flow

Presentation (13)

  • Samsung Foundry AMS Design Reference Flow - Advanced Node
  • Application of Virtuoso CurvyCore Technology in the Development of Photonic Elements for a Foundry Process Design Kit (PDK)
  • Current Data-Driven Analog Routing Using Virtuoso SDR
  • On the Silicon Photonics Physical Design’s Productivity and Reliability Enhancement
  • Useful Utilities and Helpful Hacks
  • Dragon Unleashed: Voice to Virtuoso Environment
  • Samsung 3nm Cadence AMS Design Reference Flow
  • CLE Layout Development Methodologies to Enhance Productivity of Full Custom I/O and Test-Chip Design
  • Advanced Custom Layout Methodologies
  • New Virtuoso Design Platform
  • Technology Update: Virtuoso Design Platform 20.1 Update
  • Advanced Layout Implementation Utilizing Analog APR Flow
  • Automated VDR Tagging and Verification Flow for Advanced Node Design

Datasheet (4)

  • Virtuoso Layout Suite GXL Datasheet
  • Virtuoso Layout Suite L Datasheet
  • Virtuoso Layout Suite for Electrically Aware Design Datasheet

Success Story Video (3)

  • Validating Design Intent and Improving Design Quality at Micron
  • Analog Devices Raises Productivity with ModGen Tools
  • Freescale Accelerates Layout Via Constraint-Driven Design Flow

Press Releases (22)

  • Sequans Communications Adopts Cadence RF Solution to Develop Next-Generation 5G IoT Platform
  • GLOBALFOUNDRIES Collaborates with Cadence on Availability of Mixed-Signal OpenAccess PDK for 22FDX Platform to Enable Advanced Mixed-Signal and mmWave Design
  • Cadence Digital and Custom Flows Achieve Certification for TSMC N3 Process
  • Cadence to Acquire AWR Corporation from National Instruments to Accelerate System Innovation for 5G RF Communications
  • Cadence and National Instruments Enter into Strategic Alliance Agreement to Enhance Electronic System Innovation
  • Cadence Custom/AMS Flow Certified for Samsung 5LPE Process Technology
  • Cadence Design Solutions Certified for TSMC-SoIC Advanced 3D Chip Stacking Technology
  • Cadence Collaborates with TSMC to Accelerate 5nm FinFET Innovation, Enabling Next-Generation SoC Production Design
  • Cadence Custom/AMS Flow Certified on Samsung 7LPP Process Technology
  • Cadence Achieves EDA Certification for TSMC 5nm and 7nm+ FinFET Process Technologies to Facilitate Mobile and HPC Design Creation
  • Cadence Supports New TSMC WoW Advanced Packaging Technology
  • Cadence Full-Flow Digital and Signoff Tools and Custom/Analog Tools Certified and Enabled for Intel 22FFL Process Technology
  • Cadence Tools and Flows Achieve Production-Ready Certification for TSMC’s 12FFC Process
  • Cadence Collaborates with TSMC to Advance 7nm FinFET Plus Design Innovation
  • Cadence Custom/Analog and Full-Flow Digital and Signoff Tools Enabled for GLOBALFOUNDRIES 7LP Process Node
  • Cadence Custom/Analog, Digital and Signoff Tools Achieve Certification on Samsung 28FDS Process Technology
  • Cadence Digital, Signoff and Custom/Analog Tools Enabled on Samsung’s 7LPP and 8LPP Process Technologies
  • Cadence Unveils Next-Generation Virtuoso Platform Featuring Advanced Analog Verification Technologies and 10X Performance Improvements Across Platform
  • Silicon Labs Significantly Reduces Design Time Using the Cadence Mixed-Signal Low-Power Flow
  • Cadence Collaborates with Lumerical and PhoeniX Software to Offer Virtuoso Platform-Based Design Flow for Electronic /Photonic ICs
  • Cadence Unveils Virtuoso Advanced-Node Platform for 10nm Processes
  • Cadence and Intel Collaborate to Release 14nm Library Characterization Reference Flow for Customers of Intel Custom Foundry

Webinar (10)

  • CadenceTECHTALK: Maximizing Custom Layout Productivity even as the Circuit Changes
  • Improve Device Matching with Assisted Component P&R
  • How Row-Based Methodology Improves Custom Layout
  • Using Row-Based Methodology to Improve Advanced-Node Custom Layout
  • Minimize Layout Iterations and ​ EM Errors with Simulation-Driven Routing
  • Advanced Methodologies to Accelerate Your Custom Layout
  • Webinar: Improving Custom Layout with Advanced Design Methodologies - Session Two
  • Webinar: Improving Custom Layout with Advanced Design Methodologies - Session One
  • Remove Custom Layout Bottlenecks with Concurrent Editing

Customer Presentation (3)

  • Analog Layout Automation Flow Aimed to Improve Process Porting Efficiency with Virtuoso ModGen Framework
  • Enhancing Design Productivity by Managing RV and Parasitic Data in Real Time During Layout Implementation
  • Increase Layout Productivity Through Accurate Area Estimation for Schematic Hierarchy

White Paper (1)

  • Addressing the Challenges of Photonic IC Design Via an Integrated Electronic/Photonic Design Automation Environment, Addressing the Challenges of Photonic IC Design Via an Integrated Electronic/Photonic Design Automation Environment White Paper
VIEW ALL
Videos

Samsung Foundry AMS Design Reference Flow - Advanced Node

Application of Virtuoso CurvyCore Technology in the Development of Photonic Elements for a Foundry Process Design Kit (PDK)

Current Data-Driven Analog Routing Using Virtuoso SDR

On the Silicon Photonics Physical Design’s Productivity and Reliability Enhancement

Dragon Unleashed: Voice to Virtuoso Environment

Samsung 3nm Cadence AMS Design Reference Flow

Design Intent Brings Efficient Communication in Analog Design

Analog Layout Automation Flow Aimed to Improve Process Porting Efficiency with Virtuoso ModGen Framework

From The Best Usage Of Advanced Virtuoso Functionalities

News ReleasesVIEW ALL
  • Sequans Communications Adopts Cadence RF Solution to Develop Next-Generation 5G IoT Platform 06/10/2021

  • GLOBALFOUNDRIES Collaborates with Cadence on Availability of Mixed-Signal OpenAccess PDK for 22FDX Platform to Enable Advanced Mixed-Signal and mmWave Design 09/24/2020

  • Cadence Digital and Custom Flows Achieve Certification for TSMC N3 Process 08/25/2020

  • Cadence to Acquire AWR Corporation from National Instruments to Accelerate System Innovation for 5G RF Communications 12/02/2019

  • Cadence and National Instruments Enter into Strategic Alliance Agreement to Enhance Electronic System Innovation 12/02/2019

Blogs VIEW ALL
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