Virtuoso Layout Suite EAD

Featuring a unique in-design electrical verification capability, the Cadence^® Virtuoso^® Layout Suite for Electrically Aware Design (EAD) enhances design team productivity and circuit performance for custom ICs.

With Virtuoso Layout Suite EAD, you’ll have the technology and methodology to avoid multiple design iterations and “over design.” You’ll be able to monitor electrical issues while your layout is created, and to electrically analyze, simulate, and verify interconnect decisions in real time. As a result, you’ll be able to achieve electrically correct-by-construction layout. The solution’s unique in-design electrical verification capability lets you reduce your circuit design cycle by up to 30 percent and achieve better chip performance in less area.

With Virtuoso Layout Suite EAD, you can save days to weeks of design time. The solution extracts interconnect parasitics in real time and works with partial designs. Layout and circuit designers will be able to collaborate more efficiently with enhanced real-time visibility into electrical issues. Because the solution works seamlessly with other tools in the Virtuoso platform, you’ll be able to capture currents and voltages from simulations run in Virtuoso Analog Design Environment, and pass this electrical information into the layout environment.

Refer to Blog post: Virtuoso Electrically Aware Design (EAD)—A New Approach to Custom/Analog Layout