Key Benefits
- Capture SiP module and IC schematics across multiple technologies and fabrics of design
- Multi-technology and multi-PDK support in a single Virtuoso environment
- Edit-in-Concert technology offers simultaneous layout editing of SiP module and ICs across multiple technologies and PDKs
- Interoperability with Allegro Package Designer Plus SiP Layout Option to streamline design to manufacturing
The Edit-in-Concert™ technology in the Cadence® Virtuoso® RF Solution lets designers edit across layouts and view the changes immediately at the system level within the Virtuoso environment. It enables RFIC and SIP module engineers to edit their layout design in the context of all ICs on the module or other fabrics (chip, module, board), making sure connectivity between bumps or bond wires are always correct, manufacturable and accurate.
The bidirectional interoperability between the Virtuoso Layout Suite and the SiP Layout Option solution helps automate an otherwise manual and error-prone efforts using other solutions. This helps to simplify the SiP module physical verification flow for DRC and DFM checking, with layout versus schematic (LVS) and layout versus abstract (LVA) checking tasks needed to guarantee design readiness for manufacturing.
Watch an RF demo showing the extraction of an inductor from layout and the impact on circuit simulation of a VCO.
