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Digital Design and Signoff

Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.

PRODUCT CATEGORIES

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Custom IC / Analog / RF Design

Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.

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Verification

Offering a full verification flow to our customers and partners that delivers the highest verification throughput in the industry

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IP

An open IP platform for you to customize your app-driven SoC design.

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IC Package Design and Analysis

Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.

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Multiphysics System Analysis

Cadence® system analysis solutions provide highly accurate electromagnetic extraction and simulation analysis to ensure your system works under wide-ranging operating conditions.

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Embedded Software

PCB Design and Analysis

Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.

PRODUCT CATEGORIES

  • Design Authoring
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Computational Fluid Dynamics

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US - English
  • China - 简体中文
  • Japan - 日本語
  • Korea - 한국어
  • Taiwan - 繁體中文
  • Products
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Integrity 3D-IC Platform
          • Cadence Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Voltus IC Power Integrity Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Spectre FX Simulator
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus-Fi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Virtual Prototyping
          • Emulation and Prototyping
          • Static and Formal Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
      • IP
        • PRODUCT CATEGORIES
          • 112G/56G SerDes
          • Chiplet and D2D
          • Denali Memory Interface and Storage IP
          • Interface IP
          • PCIe and CXL
          • Tensilica Processor IP
        • RESOURCES
          • Discover PCIe
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
      • Multiphysics System Analysis
        • PRODUCT CATEGORIES
          • Computational Fluid Dynamics
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Signal and Power Integrity
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Solver Cloud
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Fidelity CFD
          • Sigrity Advanced SI
          • Celsius Advanced PTI
          • RESOURCES
          • System Analysis Center
          • System Analysis Resources Hub
          • AWR Free Trial
      • Embedded Software
      • PCB Design and Analysis
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • Allegro X Design Platform
          • RESOURCES
          • What's New in Allegro
          • Advanced PCB Design & Analysis Resources Hub
          • Flows
      • Computational Fluid Dynamics
    • PERVASIVE INTELLIGENCE
      • AI / Machine Learning
      • AI IP Portfolio
    • CADENCE CLOUD
    • VIEW ALL PRODUCTS
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      • Technologies
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        • Advanced Node
        • AI / Machine Learning
        • Arm-Based Solutions
        • Cloud Solutions
        • Computational Fluid Dynamics
        • Functional Safety
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • Industries
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • Hyperscale Computing
      • Technologies
        • 3D-IC Design
        • Advanced Node
        • AI / Machine Learning
        • Arm-Based Solutions
        • Cloud Solutions
        • Computational Fluid Dynamics
        • Functional Safety
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • Industries
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • Hyperscale Computing
      • Technologies
        • 3D-IC Design
        • Advanced Node
        • AI / Machine Learning
        • Arm-Based Solutions
        • Cloud Solutions
        • Computational Fluid Dynamics
        • Functional Safety
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
  • Support
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        • Support Process
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        • Support Process
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Virtuoso RF Solution Layout Co-Design

Edit-in-Concert simultaneous editing of IC and SiP modules

Read White Paper Free Trial
  • Virtuoso RF Solution Overview
  • Layout Co-Design
  • Electromagnetic Analysis
  • Circuit Simulation

Key Benefits

  • Capture SiP module and IC schematics across multiple technologies and fabrics of design
  • Multi-technology and multi-PDK support in a single Virtuoso environment
  • Edit-in-Concert technology offers simultaneous layout editing of SiP module and ICs across multiple technologies and PDKs
  • Interoperability with Allegro Package Designer Plus SiP Layout Option to streamline design to manufacturing

The Edit-in-Concert™ technology in the Cadence® Virtuoso® RF Solution lets designers edit across layouts and view the changes immediately at the system level within the Virtuoso environment.  It enables RFIC and SiP module engineers to edit their layout design in the context of all ICs on the module or other fabrics (chip, module, board), making sure connectivity between bumps or bond wires are always correct, manufacturable and accurate.

virtuoso-rf-solution-co-design-600px
Edit in Concert co-design environment for SiP and IC layout

The bidirectional interoperability between the Virtuoso Layout Suite and the SiP Layout Option solution helps automate an otherwise manual and error-prone efforts using other solutions. This helps to simplify the SiP module physical verification flow for DRC and DFM checking, with layout versus schematic (LVS) and layout versus abstract (LVA) checking tasks needed to guarantee design readiness for manufacturing.

virtuoso-rf-solution-layer-interop-sip-600px
Interoperability between Virtuoso Layout Suite and Cadence SiP Layout

TRAINING COURSES

Watch an RF demo showing the extraction of an inductor from layout and the impact on circuit simulation of a VCO.

  • Related Products

    • Virtuoso Layout Suite
    • Allegro Package Designer Plus SiP Layout Option
    • Spectre RF Option
    • Clarity 3D Solver
Videos

Sequans Designs its Future 5G IoT Platform Using Virtuoso RF Solution

A Better Multi-Fabric RF Design Flow

Virtuoso RF Solution Electromagnetic Analysis

Take a Test Drive with Our Free Trial ​

Module Layout with​ Edit-in-Concert️ Technology

Use Virtuoso RF Solution to implement a multi-chip module.​ Work in a schematic-driven and connectivity-driven flow by capturing the multi-chip-module (SiP) logic connectivity using Virtuoso Schematic Editor. Enable a co-design layout flow using Virtuoso Layout Suite and interoperability with SiP Layout Option.

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EM Solver in Virtuoso Layout Suite​

Run EM analyses directly from Virtuoso Layout Suite and manage all EM models in the layout view.​ Use EM models in circuit simulation by leveraging intelligent model stitching and combine RC parasitic with EM modeling in circuit simulations.

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Cadence Online Support​ Rapid Adoption Kits​

Log in to Cadence Online Support where you can get help from Cadence experts and our extended design community. You also can find Rapid Adoption Kits (RAK) on RF design and other topics for self-paced learning.​

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  • Cadence Furthers Expansion in 5G RF Communications with Acquisition of Integrand 02/13/2020

  • Cadence Completes Acquisition of AWR Corporation from National Instruments 01/15/2020

  • Cadence to Acquire AWR Corporation from National Instruments to Accelerate System Innovation for 5G RF Communications 12/02/2019

  • Cadence and National Instruments Enter into Strategic Alliance Agreement to Enhance Electronic System Innovation 12/02/2019

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