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Digital Design and Signoff

Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.

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  • Products
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Genus Synthesis Solution
          • Conformal Smart LEC
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Virtuoso RF Solution
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus IC Power Integrity Solution
          • RESOURCES
          • Flows
      • Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Emulation and Prototyping
          • Formal and Static Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • JasperGold Formal Verification Platform
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
      • IP
        • PRODUCT CATEGORIES
          • Interface IP
          • Denali Memory IP
          • Tensilica Processor IP
          • Analog IP
          • System / Peripherals IP
          • Verification IP
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
      • System Analysis
        • PRODUCT CATEGORIES
          • Computational Fluid Dynamics
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Signal and Power Integrity
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Omnis
          • Sigrity Advanced SI
          • Sigrity Advanced PI
          • RESOURCES
          • System Analysis Center
          • System Analysis Resources Hub
          • AWR Free Trial
      • Embedded Software
      • PCB Design and Analysis
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • RESOURCES
          • What's New in Allegro
          • What's New in Sigrity
          • Advanced PCB Design & Analysis Resources Hub
          • Flows
    • PERVASIVE INTELLIGENCE
      • AI / Machine Learning
      • AI IP Portfolio
    • CADENCE CLOUD
    • VIEW ALL PRODUCTS
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        • Cloud Solutions
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
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        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • AI / Machine Learning
      • Technologies
        • 3D-IC Design
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        • RF / Microwave
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        • AI / Machine Learning
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Advanced Aging

Read Datasheet
  • Legato Reliability Solution
  • Analog Defect
  • Electrothermal
  • Advanced Aging

Key Benefits

  • Specifies process variation models and aging models together
  • Stress simulation runs 1X on nominal and re-used for all iterations
  • Looks at the results and compares how process variations impact aging
  • Flexibility to use proprietary calculations for self-heating along with aging analysis
  • Supports layout dependent effect (LDE) calculations and user-defined degradation models
  • BTI recovery effect included
  • Models incorporate HCI degradation saturation effects

Designers must find a way to accurately predict the effect of stress over the lifetime of a device, otherwise device wear-out can result in early end-of-life failure. Designers have had the enormous challenge of accounting for each source of device degradation in isolation, then using reliability analysis to estimate device degradation due to electrical stress followed by estimating the reduced lifetime based on estimated die temperature and the effect of process variation.

The Cadence® Legato™ Reliability Solution is the industry’s first solution to provide a holistic approach to reliability analysis. The solution unifies advanced aging analyses, so designers can include all the sources of device degradation in one place for their analysis including traditional electrical stress-based aging analysis, predictive models of aging effects, realistic stress conditions based on mission profiles, accelerated aging based on device operating temperature instead of the using the ambient temperature, and direct calculation of the process variation on aging instead of using estimated derating.

BTI recovery effect

Traditional aging models developed for legacy nodes and planar CMOS transistors are unable to analyze new technologies like advanced nodes and FinFET transistors. The Legato Reliability Solution is a one-stop-shop solution that provides old and new device aging models based on the most recent research in device physics to better predict device degradation due to Hot Carrier Injection (HCI) and Bias Temperature Instability (BTI). With the Legato Reliability Solution, designers are now able to better predict advanced aging analysis over the operating lifetime of their designs.

TRAINING COURSES

Explore how to extend your product lifetime by analyzing and simulating aging failures for your analog and mixed-signal design.

  • Related Products

    • Circuit Simulation
    • Spectre AMS Designer
    • Automotive Solutions
    • Virtuoso ADE Product Suite
    • Spectre Accelerated Parallel Simulator
Videos

Legato analog fault simulation for safety coverage: a case-study

Mitigating Reliability Failures Over the Product Lifespan

Designing High-Reliability Analog and Mixed-Signal ICs for Mission-Critical Applications

How to Meet the Quality, High Reliability, and Safety Requirements for Analog and Mixed-Signal ICs in Mission-Critical Applications

Analog Defect Simulation and Analysis for Complex Systems

Improvements in Modeling Device Aging Analysis: Extending Product Lifetime

Easily Adopt Electro-thermal Simulation for Your High-Reliability Analog Designs

Automotive System Trends and the Integration of Analog Electronic Dependability

News ReleasesVIEW ALL
  • Cadence to Acquire AWR Corporation from National Instruments to Accelerate System Innovation for 5G RF Communications 12/02/2019

  • Cadence Automotive Reference Flow Certified by Samsung Foundry for Advanced-Node Design Creation 10/17/2019

  • Cadence Introduces the Spectre X Simulator, a Massively Parallel Circuit Simulator Delivering Up to 10X Faster Simulation with the Same Golden Accuracy 06/03/2019

  • Cadence Debuts Industry’s First Analog IC Design-for-Reliability Solution 05/08/2018

  • Cadence Expands Virtuoso Platform with Enhanced System Design, Advanced Node Support down to 5nm, and Simulation-Driven Layout 04/10/2018

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