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Digital Design and Signoff

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  • Products
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Genus Synthesis Solution
          • Conformal Smart LEC
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Virtuoso RF Solution
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus IC Power Integrity Solution
          • RESOURCES
          • Flows
      • System Design and Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Emulation
          • Formal and Static Verification
          • FPGA-Based Prototyping
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • JasperGold Formal Verification Platform
          • Xcelium Logic Simulation
          • Palladium Z1 Enterprise Emulation Platform
          • Protium X1 Enterprise Prototyping Platform
          • System VIP
          • RESOURCES
          • Flows
      • IP
        • PRODUCT CATEGORIES
          • Interface IP
          • Denali Memory IP
          • Tensilica Processor IP
          • Analog IP
          • System / Peripherals IP
          • Verification IP
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
      • System Analysis
        • PRODUCT CATEGORIES
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Sigrity Advanced SI
          • Sigrity Advanced PI
          • RESOURCES
          • System Analysis Resources Hub
      • Embedded Software
      • PCB Design and Analysis
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • RESOURCES
          • What's New in Allegro
          • What's New in Sigrity
          • Advanced PCB Design & Analysis Resources Hub
          • Flows
    • PERVASIVE INTELLIGENCE
      • AI / Machine Learning
      • AI IP Portfolio
    • CADENCE CLOUD
    • VIEW ALL PRODUCTS
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        • Cloud Solutions
        • Low Power
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        • RF / Microwave
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        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • AI / Machine Learning
      • Technologies
        • 3D-IC Design
        • Advanced Node
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        • Low Power
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Virtuoso Variation Option

Advanced statistical exploration of your design

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Key Benefits

  • Easily enables the appropriate analysis by letting you simply choose your task (e.g., yield verification) or statistical corner creation and specify your target sigma requirement
  • Provides high-yield estimation capabilities for checking the outer boundaries of your design at the 4-, 5-, or 6-sigma level
  • Delivers advanced statistical sample reordering that greatly improves the performance of the statistical simulation, with additional speed-up for FinFET technology at 16nm and below
  • Provides mismatch contribution analysis and statistical sensitivity analysis to pinpoint most influential devices within a statistical simulation
  • Features easy, one-step creation of worst-case corners as derived by 3-sigma statistical sampling

The Cadence® Virtuoso® Variation Option extends the statistical variation capabilities of Cadence’s Virtuoso ADE Assembler and Virtuoso ADE Verifier to allow for more sophisticated statistical analyses to be performed on any design. Specialized technology is also available for advanced-node designs.

Statistical sample reordering 

Directly addresses the significant challenges associated with 3-sigma design, especially at an advanced process node or low Vdd. Virtuoso Variation Option provides a statistical approach to verify circuit yield or create corners efficiently by reordering the samples to simulate the worst samples first. The method is co-developed with major foundries to provide with additional speedup for FinFET technology at 16nm and below.

High-yield estimation for 4-, 5-, or 6-sigma analysis

Parametric high-yield estimation is often required on devices that have extremely high volume (i.e., memory devices), or when testing the circuit limits is a must when failure of the part is not an option (i.e., automotive safety or medical devices). The Virtuoso Variation Option provides two methods of simulation to meet and match your needs and conditions:

  • Scaled-sigma sampling (SSS): This preferred statistical method generates samples where the standard deviation has been scaled up which is more accurate than WCD for nonlinear behavior and more efficient when there is a large number of statistical parameters and specifications.
  • Worst-case distance (WCD): This statistical method defines the shortest distance from the nominal point to the specification boundary in the process/mismatch parameter space. WCD typically requires under 100 simulations for each spec and so is suitable for designs with a small number of specs/parameters that need to be monitored/changed.

Automated yield improvement flow

Virtuoso Variation Option has an “Improve Yield” command that will return a design to a state where it meets all of the design criteria and has the highest possible yield. If no such point has been reached it will run iterative analyses on the current criteria and determine the conditions for highest possible yield for that design.

Mismatch contribution analysis

Virtuoso Variation Option has a mismatch contribution analysis feature which is a Monte Carlo post-processing feature that helps in identifying the important contributors to mismatch variation. You can then modify the identified devices in the schematic and make the design less sensitive to mismatch variation. 

Automotive TCL1 Certified for ISO 26262

The industry’s first analog/mixed-signal design implementation and verification flow to achieve “Fit for Purpose - Tool Confidence Level 1 (TCL1)” certification enables you to meet stringent ISO 26262 automotive safety requirements. The flow brings transistor-level designs from creation and simulation through physical implementation and verification using the Virtuoso ADE Product Suite and the Spectre® Circuit Simulation Platform. The Virtuoso ADE Verifier provides design engineers with an integrated means to validate the safety specifications against individual circuit specifications for design confidence. For information on the safety manuals, Tool Confidence Analysis (TCA) documents, and compliance reports from TÜV SÜD, download the Functional Safety Documentation Kits through Cadence Online Support.

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TRAINING COURSES

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    • Virtuoso ADE Assembler
    • Virtuoso ADE Explorer
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Videos

Celebrating 25 Years of Virtuoso Innovation

Verification Made Easy: Learn How to Avoid Mistakes with Virtuoso ADE Verifier

The New Sound of Analog Design: Simplify Design Verification with Virtuoso ADE Product Suite

Easily Explore and Analyze Your Design with Virtuoso ADE Product Suite

News ReleasesVIEW ALL
  • GLOBALFOUNDRIES Collaborates with Cadence on Availability of Mixed-Signal OpenAccess PDK for 22FDX Platform to Enable Advanced Mixed-Signal and mmWave Design 09/24/2020

  • Cadence Digital and Custom Flows Achieve Certification for TSMC N3 Process 08/25/2020

  • Cadence Achieves Digital and Custom/Analog EDA Flow Certification for TSMC N6 and N5 Process Technologies 06/02/2020

  • Cadence to Acquire AWR Corporation from National Instruments to Accelerate System Innovation for 5G RF Communications 12/02/2019

  • Cadence and National Instruments Enter into Strategic Alliance Agreement to Enhance Electronic System Innovation 12/02/2019

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