Cadence® AWR® software products offer a leading front-to-back monolithic microwave integrated circuits (MMIC) design flow with an innovative user interface and complete integration of design entry, simulation, and physical design tools that enhances engineering productivity and ensures first-pass success. III-V semiconductors such as gallium arsenide (GaAs) and gallium nitride (GaN) offer superior RF performance for mobile devices, communications infrastructure, and aerospace applications. MMICs based on GaAs or GaN heterojunction bipolar transistor (HBT) and high-electron mobility transistor (HEMT) devices achieve optimal performance through reliable circuit simulation, electromagnetic (EM) verification, communication testbenches, and a design flow that links electrical design to physical realization.
- Powerful design entry with process-specific models and EM-aware layout parameterized cells (PCells)
- Accurate, fast, and robust harmonic balance (HB) simulation
- Process design kits (PDKs) for III-V semiconductor foundries
- Automated circuit extraction (ACE) technology for interconnect modeling
- Fully integrated 3D planar EM simulator for design verification and parasitic extraction of on-chip components and interconnects
- Fully integrated 3DEM simulator for analysis of bumps, bond wires, and ribbons
- System co-simulation for circuit envelope analysis and wireless standards verification
- Electrical rule check (ERC), design rule check (DRC), and layout versus schematic (LVS) support production-ready GDSII export
Design Entry and Management
MMICs integrate active devices within a network of on-chip passive components to provide the functionality necessary for desired performance. Electrical behavior is directly linked to the physical attributes of individual on-chip components, as well as the overall chip layout. A comprehensive MMIC design flow provides parametric, process-specific on-chip component models and layout PCells to support accurate simulations, and a layout that complies with foundry manufacturing rules. Design automation and powerful scripting enable MMIC designers to be more productive by eliminating manual design efforts and excessive data import/export, as well as supporting tool customization for every special design consideration.
Simulation for RF Front-End Applications
RF/microwave electronics rely on specialized measurements such as noise figure (NF) and S-parameters, as well as the nonlinear power, gain compression, and efficiency response to large-signal stimuli. RF simulation uses frequency-domain HB analysis to analyze nonlinear networks, including power amplifiers (PAs) and frequency converters (mixers). With digital modulation for communications systems, designers also may need to analyze MMICs with circuit envelope techniques to simulate metrics such as adjacent-channel power-ratio (ACPR) and error-vector magnitude (EVM).
Model Support from Leading Foundries
GaAs, GaN, and silicon germanium (SiGe) semiconductors continue to evolve in support of MMICs operating at higher millimeter-wave (mmWave) frequencies for communications and radar applications, while also offering improved performance across all frequencies. Software vendors such as Cadence must work closely with leading III-V semiconductor foundries and load-pull test system manufacturers to ensure the latest devices offer robust, simulation-ready models for design.
MMIC designers rely on circuit/EM co-simulation, along with RF-aware circuit simulation and frequency-dependent transmission-line models, to provide embedded parasitic extraction and design verification. With hierarchical EM/circuit/system co-simulation, designers can perform in-situ EM analysis to capture and correct harmful parasitic couplings and resonances before tapeout.
Cadence AWR software and system analysis products offer a leading front-to-back MMIC design flow with an innovative user interface and complete integration of design entry, simulation, and physical design tools that enhances engineering productivity and ensures first-pass success.
The AWR Design Environment® platform provides RF/microwave engineers with integrated high-frequency circuit, system, and EM simulation technologies and design automation to develop physically realizable electronics ready for manufacturing.
AWR Microwave Office® circuit design software offers an intuitive interface, innovative design automation, and powerful HB circuit simulation to ensure greater engineering productivity and accelerated design cycles.
AWR Visual System Simulator™ (VSS) RF/wireless communications and radar system design software supports voltage standing-wave ratio (VSWR)-aware modeling of RF and digital signal processing blocks, providing time-domain, frequency-domain, and circuit-envelope analyses. Simulation with preconfigured and/or customized system testbenches provides analysis of ACPR, BER, and EVM for PCBs operating under wireless, standards-specific, modulated waveforms.
The AWR AXIEM® 3D proprietary full-wave planar EM simulator is based on method-of-moments (MoM) fast-solver technology that readily analyzes distributed PCB components, transmission lines, and layer-to-layer PCB interconnects such as vias. Designers can extract S-parameters directly within their PCB design and visualize fields/currents to identify parasitic coupling and resonances.
Industry-leading Cadence distributed multiprocessing technology enables the finite element method (FEM)/finite-difference time-domain (FDTD) Clarity™ 3D Solver to deliver virtually unlimited capacity and the 10X speed required to efficiently and effectively address these larger and more complex structures. It creates highly accurate S-parameter models for use in RF/microwave, signal integrity (SI), power integrity (PI), and electromagnetic compliance (EMC) analyses.
MMIC Layout Tools
AWR Design Environment and Cadence® Virtuoso® platforms combine to bring your innovative wireless designs to life. With a comprehensive, powerful, and easy-to-use suite of tools, you can effortlessly tackle the simplest or most complex projects.
Design for manufacturing (DFM) is inherent in the AWR software platform, providing accurate modeling of process-specific metal traces and on-chip components from foundry-authorized PDKs. Export of GDSII layout files supports the transfer of design information into dedicated manufacturing tools. PDKs developed in collaboration with leading MMIC foundries provide engineers using AWR Design Environment software with schematics, scalable layout PCells, advanced layout utilities, and connectivity checking/highlighting.
The industry-leading Virtuoso custom IC layout design tools accelerate your physical layout implementation productivity, enabling you to achieve faster design convergence with higher quality and more differentiated silicon. Our Virtuoso layout design tools support full custom analog, digital, RF, and mixed-signal designs at the device, cell, block, and chip levels.
Virtuoso layout design tool capabilities incrementally build upon each other to help you manage the growing complexity of designs:
- Advanced full custom polygon editing
- Full custom layout
- Flexible schematic-driven layout
- Physical constraint-driven layout
- Electrical constraint-driven layout
- Assisted full custom layout
- Automated full custom layout