- Supports a constraint-driven mixed-signal environment
- Ability to view the complete mixed-signal design in a digital environment
- Improved pin optimization for the analog and digital blocks
- Seamless data transfer between analog and digital designers
- ECOs that can be implemented in either environment
- Late-stage ECOs on the analog or digital blocks do not disrupt chip finishing
- Chip-assembly routing with support for analog and high-capacity digital needs
Accelerating demand for new products and shortening lifecycles means design integration can no longer wait until all the blocks are finished. The Cadence® Mixed-Signal-on-Top (MSoT) methodology offers a concurrent design approach where floorplanning can start in the Virtuoso® Custom Design Platform before the RTL is available, updates to A/D interfaces are done in either the Virtuoso platform or the Innovus™ Implementation System, and changes to blocks can occur early and often, all of which help your design team create products with less risk and better turnaround time.
As shown in the flow diagram, the MSoT methodology is a concurrent and collaborative development process. While this new methodology supports the separation of the analog and digital design teams and tools, responsibility for the overall design progress is coordinated between the design teams. Top-level floorplanning becomes a joint exercise of optimizing area and changing pin-outs and routing nets as needed, until both groups can sign off on the floorplan. Floorplanning is truly mixed-signal oriented, with the flexibility to assign or optimize pins in either the Virtuoso or Innovus platforms. This flexibility reduces iterations and results in better floorplans, smaller area, less routing congestion, and earlier chip finishing with faster overall turnaround times.
Once the floorplan is complete, analog and digital block implementations occur in the appropriate design environment. Top-level implementation and chip assembly, like floorplanning, becomes a continuous and shared exercise between the analog and digital teams, with necessary readjustments made on either side.
Digital designers using the Innovus Implementation System have full visibility into PCELL layouts for analog blocks. The Virtuoso Space-Based Router performs top-level mixed-signal routing and manages analog constraints such as shielding, matching, differential pairs, and bus routing, which are recognized and honored in the Innovus Implementation environment, as well.
The Cadence mixed-signal solution, using OpenAccess, offers seamless access to all design data, and leverages the strengths of the Virtuoso and Innovus platforms to increase overall design efficiency and throughput. Key advantages of this solution include the ability to start top-level floorplanning in the Virtuoso platform even before the RTL is ready, thereby saving time; analog devices and gates in the same hierarchy; and a constraint-driven routing methodology across hierarchies, power domains, and IPs.