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- Augmenting Simulation Via Low-Power Verification Methodologies with Emulation
- Low-Power Mixed-Signal Verification of Freescale Kinetis Products
- UVM methodology based Verification Environment for Imaging IPs/SoCs
- Closing Gaps in Mixed-Signal Power Implementation Using a Consistent Power Intent
- Developing 4G Wireless Designs with Cadence CPF-Driven Low-Power Solution
- Accurate Low Power verification on a Complex Low Power Design using CLP
- Freeescale Semiconductor - Cadence Low-Power Solution for Kinetis SoC
- Low Power Verification USING CPF/IEEE 1801 and Application of Formal Verification at Chip Level
- X-FAB Revamps Low-Power Design Flow with CPF
- Detecting System-Level Corner Cases During Low-Power SoC Verification
- Detecting Low-Power Bugs with X-Optimism Simulation
- Lowering Leakage Power in ARM Cortex-A17 Processor-based SoCs at GLOBALFOUNDRIES
- Low-Power Summit ARM Sathya Subramanian
- Design Challenges in Developing Sub-Volt IP Designs for IoT Applications
- Introducing Low-power Verification RAK
- PMC - Power Estimation – An Evolving Science
- Plan-Driven Low-Power Verification and Debugging at STMicroelectronics
- MediaTek Gets High-Quality Smart Devices to Market Quickly with Palladium Platform
- 5 Steps to Your First Power Shut-off (PSO) Verification
- 6 Must Know Tips to Optimize LPDDR and Wide I/O Performance
- System Level Low Power Verification Using Palladium and CPF
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