- Comprehensive solution for low power including architecture optimization, power estimation and analysis, functional verification, implementation and signoff, and IP for digital and mixed-signal designs at both chip and system level
- Support for both industry-standard power intent formats (CPF and IEEE 1801), enabling customers to adopt the design flow of their choice
- Production proven on thousands of designs mitigating risk of re-spins, reducing product development time and costs
With the emergence of wearables, smart appliances for home, industrial automation, automotive electronics, and big data processing, low-power design is no longer confined to the mobile device end markets. Power management touches every aspect of the design flow, from the architectural stage to chip and system signoff. Consequently, EDA tools have to take a holistic approach to low-power design.
The Cadence® low-power solution considers power at every step of the design flow, from architecture to functional verification, analysis, implementation, and signoff.
High-level synthesis (HLS) methodology users benefit from the power-aware architectural/micro-architectural choices available from a very high-level description of the design. This supports making the right trade-offs for power, performance, and area (PPA) at the earliest stages of the design when it matters the most.
Once the RTL and power intent are available for analysis, the Cadence solution helps perform a sanity check of the power intent itself. This prevents unexpected surprises as the designer progresses through the low-power flow. The Cadence solution supports both the IEEE 1801 and CPF industry-standard formats for power intent. Simulation, emulation, and formal verification tools from Cadence are power-aware and verify the design interactions between functional and power modes in which the design is meant to operate. This helps to eliminate hard-to-find design or power intent bugs that could potentially cause chip and system failures in the field.
All aspects of implementation consider the power intent and make trade-offs and optimizations for leakage and dynamic power to deliver a low-power design with high Quality of Results (QoR). At every stage of implementation, the Cadence solution helps verify that the low-power design is compliant with the specified power intent. Signoff tools are power intent-driven as well, ensuring that the power intent has been implemented correctly to avoid re-spins and product delays and reduce product costs.
The Cadence low-power solution has also built links between the chip and system level to verify that the power integrity of the entire system is achieved in the context of the chip, board, and package.
Cadence has enabled the low-power flow for mixed-signal designs as well. Intellectual property (IP) in the form of embedded customizable processor cores and interface IP optimized for power consumption is available from Cadence.
Finally, the Cadence low-power solution has been used in production in thousands of designs.
- Augmenting Simulation Via Low-Power Verification Methodologies with Emulation
- Low-Power Mixed-Signal Verification of Freescale Kinetis Products
- UVM methodology based Verification Environment for Imaging IPs/SoCs
- Closing Gaps in Mixed-Signal Power Implementation Using a Consistent Power Intent
- Developing 4G Wireless Designs with Cadence CPF-Driven Low-Power Solution
- Accurate Low Power verification on a Complex Low Power Design using CLP
- Freeescale Semiconductor - Cadence Low-Power Solution for Kinetis SoC
- Low Power Verification USING CPF/IEEE 1801 and Application of Formal Verification at Chip Level
- X-FAB Revamps Low-Power Design Flow with CPF
- Lowering Leakage Power in ARM Cortex-A17 Processor-based SoCs at GLOBALFOUNDRIES
- Detecting Low-Power Bugs with X-Optimism Simulation
- MediaTek Gets High-Quality Smart Devices to Market Quickly with Palladium Platform
- 5 Steps to Your First Power Shut-off (PSO) Verification
- 6 Must Know Tips to Optimize LPDDR and Wide I/O Performance
- System Level Low Power Verification Using Palladium and CPF
- Low-Power Summit ARM Sathya Subramanian
- Introducing Low-power Verification RAK
- PMC - Power Estimation – An Evolving Science
- Design Challenges in Developing Sub-Volt IP Designs for IoT Applications
- Plan-Driven Low-Power Verification and Debugging at STMicroelectronics
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