Today’s hyperscale computing challenges have evolved—especially in hyperscale data centers—from the homogeneous compute of the last decades to workload-optimized and heterogeneous computing.

Storage and networking that enabled latencies in the millisecond range now must support microsecond latencies. Designers are actively considering moving away from costly and time-consuming monolithic systems on chip (SoCs) and derivatives as design sizes are approaching or exceeding the reticle size, causing yield issues. 

Not only does the usage of chiplets and 2.5D/3D-IC packaging address these SoC challenges, they also allow faster creation of derivatives and enable more design options. 

Optimized advanced-node implementation is a must, and co-optimization of hardware and software using prototyping and emulation replaces the siloed optimization of silicon, modules, and software of the past, allowing optimization for low-power aspects at the earliest possible stages during design flows, as well as enablement of artificial intelligence / machine learning (AI/ML) chips and systems as combinations of hardware and software.

Chiplet-Based Design for 3D-IC

To meet the demand of growing design complexities, design teams consider integration of memory, computing, and dedicated accelerators in packages versus on-chip. This approach also enables fast, flexible derivatives. Cadence offers a comprehensive product portfolio for 3D-IC design, from chiplet-related IP, through verification, digital and analog implementation flows, and multi-domain system analysis.

Multi-domain system analysis is enabled by the Cadence® system analysis portfolio. For instance, analyzing thermal effects is a must because the through-silicon-vias (TSVs) in 3D-ICs can result in poor lateral heat distribution, more heat dissipation, and reduced performance if not managed properly. New test strategies are required, and package silicon co-design becomes critical. In addition, having computational fluid dynamics (CFD) products, such as the Cadence OMNIS™ suite, to simulate, design, and optimize in one multiphysics CFD environment is essential to assess the integration of chips into boards and systems.

At the core of the solution for 3D-IC design implementation, planning, and analysis is the Cadence® Integrity 3D-IC Platform for designing multiple chiplets. Built on the infrastructure of Cadence’s leading digital implementation capabilities, the platform allows system-level designers to plan, implement, and analyze any type of stacked die system for a variety of packaging styles (2.5D or 3D). It provides a 3D-IC stack planning system, seamlessly integrates through scripts with Cadence Innovus™ Implementation System and OrbitIO™ Interconnect Designer, and provides integrated system-level analysis capabilities for robust 3D-IC design through early electrothermal and cross-die static timing analysis (STA). A common cockpit and database lets SoC and package design teams co-optimize the complete system concurrently, allowing system-level feedback to be incorporated efficiently.

For signoff and analysis of 3D-ICs, the Quantus™ Extraction Solution provides parasitic extraction, the Tempus™ Timing Signoff Solution provides silicon-accurate timing signoff and signal integrity analysis across multiple dies, and the Voltus™ IC Power Integrity Solution addresses full-chip, multi-die, 3D-IC system-in-package (SiP) analysis.

Verification for Hyperscale Computing

The Cadence Verification Suite provides optimal verification throughput and simulation, emulation, prototyping, formal verification, verification planning, debug and test automation. Using system performance analysis, developers can analyze the effects of AI/ML software workloads on specific design architectures for early hardware/software co-development. With hybrid emulation and prototyping, developers can create relevant controlled scenarios with software models of AI processors. Verification IP (VIP) optimized for data center designs allows driving traffic for IP and subsystem verification.

Dynamic power analysis, combining verification and implementation tools, allows analysis of power trends while running AI/ML workloads. The comprehensive solution for low power, including architecture optimization, power estimation and analysis, functional verification, implementation and signoff, and IP for digital and mixed-signal designs at both chip and system levels. Our offerings support both industry-standard power intent formats (CPF and IEEE 1801), enabling customers to adopt the design flow of their choice, and are production-proven on thousands of designs, mitigating the risk of respins and reducing product development time and costs.

Design IP for Hyperscale Computing

As the design paradigm extends from the reuse of IP to reuse of chiplets, critical driving applications fueling this trend include the complexity of multicore processors, general-purpose GPUs, the combination of processors, and workload accelerators well as scientific computing. In memory and storage HBM cache extensions, processing in memory (PIM), packet buffering and look-ups, and data analytics further amplify the trend towards 3D-IC integration. Connectivity with the integration of hosts, client and I/O peripherals, networks on chip (NOCs) with interposers, server chips combining CPUs and chipset, and web servers also benefit from chiplets and heterogeneous 3D-IC integration. Cadence offers a broad portfolio of pulse amplitude modulation 4-level (PAM4) and chiplet-based PHY IP that allows design teams to optimize their implementations across the metrics package cost and yield, bandwidth, and signaling using non-return-to-zero (NRZ) versus PAM4 serial interfaces, power, and latency. The Cadence IP portfolio enables typical designs with 2.5D interposers for HBM, 112G SerDes providing chip-to-line connectivity, and D2D or HBI interfaces between I/O chiplets and the core. Designers can choose intra-package interconnect IP options with varying speeds from 40 NRZ UltraLink D2D IP to 112G PAM4 112G-XSR and 4.8G NRZ HBI.