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Digital Design and Signoff

Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.

PRODUCT CATEGORIES

  • Logic Equivalence Checking
  • SoC Implementation and Floorplanning
  • Functional ECO
  • Low-Power Validation
  • Synthesis
  • Power Analysis
  • Constraints and CDC Signoff
  • Silicon Signoff and Verification
  • Library Characterization
  • Test

FEATURED PRODUCTS

  • Genus Synthesis Solution
  • Conformal Smart LEC
  • Innovus Implementation System
  • Tempus Timing Signoff Solution
  • Pegasus Verification System
  • RESOURCES
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Custom IC / Analog / RF Design

Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.

PRODUCT CATEGORIES

  • Circuit Design
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  • Layout Design
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  • RF / Microwave Solutions

FEATURED PRODUCTS

  • Spectre X Simulator
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System Design and Verification

Cadence® system design and verification solutions, integrated under our Verification Suite, provide the simulation, acceleration, emulation, and management capabilities.

PRODUCT CATEGORIES

  • Debug Analysis
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  • Simulation
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  • Verification IP
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FEATURED PRODUCTS

  • vManager Verification Management
  • JasperGold Formal Verification Platform
  • Xcelium Logic Simulation
  • Palladium Z1 Enterprise Emulation Platform
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  • System VIP
  • RESOURCES
  • Flows

IP

An open IP platform for you to customize your app-driven SoC design.

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  • Interface IP
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IC Package Design and Analysis

Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.

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  • Cross-Platform Co-Design and Analysis
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System Analysis

Cadence® system analysis solutions provide highly accurate electromagnetic extraction and simulation analysis to ensure your system works under wide-ranging operating conditions.

PRODUCT CATEGORIES

  • Electromagnetic Solutions
  • RF / Microwave Design
  • Thermal Solutions

FEATURED PRODUCTS

  • Clarity 3D Solver
  • Clarity 3D Transient Solver
  • Celsius Thermal Solver
  • Sigrity Advanced SI
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  • RESOURCES
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Embedded Software

PCB Design and Analysis

Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.

PRODUCT CATEGORIES

  • Design Authoring
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  • Library and Design Data Management
  • Analog/Mixed-Signal Simulation
  • SI/PI Analysis
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  • RF / Microwave Design
  • Augmented Reality Lab Tools

FEATURED PRODUCTS

  • Allegro Package Designer Plus
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US - English
  • China - 简体中文
  • Japan - 日本語
  • Korea - 한국어
  • Taiwan - 繁體中文
  • Products
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Genus Synthesis Solution
          • Conformal Smart LEC
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Virtuoso RF Solution
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus IC Power Integrity Solution
          • RESOURCES
          • Flows
      • System Design and Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Emulation
          • Formal and Static Verification
          • FPGA-Based Prototyping
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • JasperGold Formal Verification Platform
          • Xcelium Logic Simulation
          • Palladium Z1 Enterprise Emulation Platform
          • Protium X1 Enterprise Prototyping Platform
          • System VIP
          • RESOURCES
          • Flows
      • IP
        • PRODUCT CATEGORIES
          • Interface IP
          • Denali Memory IP
          • Tensilica Processor IP
          • Analog IP
          • System / Peripherals IP
          • Verification IP
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
      • System Analysis
        • PRODUCT CATEGORIES
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Sigrity Advanced SI
          • Sigrity Advanced PI
          • RESOURCES
          • System Analysis Resources Hub
      • Embedded Software
      • PCB Design and Analysis
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • RESOURCES
          • What's New in Allegro
          • What's New in Sigrity
          • Advanced PCB Design & Analysis Resources Hub
          • Flows
    • PERVASIVE INTELLIGENCE
      • AI / Machine Learning
      • AI IP Portfolio
    • CADENCE CLOUD
    • VIEW ALL PRODUCTS
  • Solutions
      • Industries
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • AI / Machine Learning
      • Technologies
        • 3D-IC Design
        • Advanced Node
        • Arm-Based Solutions
        • Cloud Solutions
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • Industries
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • AI / Machine Learning
      • Technologies
        • 3D-IC Design
        • Advanced Node
        • Arm-Based Solutions
        • Cloud Solutions
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • Industries
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • AI / Machine Learning
      • Technologies
        • 3D-IC Design
        • Advanced Node
        • Arm-Based Solutions
        • Cloud Solutions
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
  • Support
      • Support
        • Support Process
        • Online Support
        • Software Downloads
        • Computing Platform Support
        • Customer Support Contacts
        • Technical Forums
      • Training
        • Custom IC / Analog / RF Design
        • Languages and Methodologies
        • Digital Design and Signoff
        • IC Package
        • PCB Design
        • System Design and Verification
        • Tensilica Processor IP
      • Support
        • Support Process
        • Online Support
        • Software Downloads
        • Computing Platform Support
        • Customer Support Contacts
        • Technical Forums
      • Training
        • Custom IC / Analog / RF Design
        • Languages and Methodologies
        • Digital Design and Signoff
        • IC Package
        • PCB Design
        • System Design and Verification
        • Tensilica Processor IP
      • Support
        • Support Process
        • Online Support
        • Software Downloads
        • Computing Platform Support
        • Customer Support Contacts
        • Technical Forums
      • Training
        • Custom IC / Analog / RF Design
        • Languages and Methodologies
        • Digital Design and Signoff
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FPGA Development

Comprehensive Flow for Complex FPGAs

Key Benefits

  • From system design, to verification, to board implementation flow
  • Scalable verification methodology
  • Native integration into FPGA vendor flows
  • Complete set of tools and methodologies for DO-254 compliance
  • Methodology and tool support for DO-254 verification requirements traceability

Due to the ever-increasing costs of development and manufacturing of custom IC devices as well as the flexibility that FPGAs provide, many system houses use FPGA devices not just for prototype or early availability runs, but for the entire life of the product. The result is the number of designs that are implemented in FPGAs is growing, and the complexity of those designs is increasing, requiring more powerful EDA tools for design, up-front verification, debug, and implementation.

Cadence offers a variety of tools and methodologies that enable users to develop their FPGA designs quickly and effectively to improve quality and time to FPGA signoff. Our tools and our FPGA vendor relationships help users avoid long programming and field testing cycles.

Let us help you:

  • Track and sign off top-level requirements through all transformations for safety
  • Use techniques and methodologies to improve design productivity
  • Improve design creation and reuse of code
  • Implement system synthesis that feeds FPGA synthesis tools
  • Integrate coverage between formal and simulation increase coverage

Our portfolio includes:

  • Ability to track requirements through signoff for high-reliability, safety-critical, or any complex FPGA design projects with the vManager™ Metric-Driven Signoff Platform
  • Automatic creation of high-quality register-level (RTL) design implementations for FPGA designs with Stratus™ High-Level Synthesis
  • Broad memory and protocol support with Cadence® design IP, memory IP, and verification IP (VIP)
  • Formal verification through JasperGold® Apps to find more bugs in less time and earlier in the design process
  • High-performance simulation with comprehensive VHDL, SystemVerilog, and other language support with the Xcelium™ Parallel Logic Simulator
  • Rapid prototyping with debug and emulation congruence with Protium™ S1 FPGA-Based Prototyping Platform
  • Fast system debug, acceleration, and emulation with Palladium® Z1 Enterprise Emulation Platform
  • Rapid generation of system stimulus with the Perspec™ System Verifier
  • Automatic pin assignment synthesis for rapid PCB development with the Allegro® FPGA System Planner

 

FPGA Flow
  • Related Products

    • Allegro FPGA System Planner
    • JasperGold Formal Verification Platform
    • Palladium Z1 Enterprise Emulation Platform
    • Perspec System Verifier
    • Protium S1 Desktop Prototyping Platform
    • Stratus High-Level Synthesis
    • Verification IP
    • vManager Verification Management
    • Xcelium Logic Simulation
Resource Library

Video (10)

  • New Cadence Products Expand the Verification Suite: Xcelium Parallel Simulator and Protium S1 Platform
  • Faster Routing by Optimizing FPGA Pin Assignments
  • Protium S1 used to prototype a pedestrian detection application.
  • Faster HW/SW Debug, Embedded Software Development and System Validation
  • Xilinx - Industry Leading Solutions for FPGA-based Prototyping
  • Accelerating design-in of Xilinx FPGAs while optimizing PCB layout for cost and performance
  • Accelerating design-in of Altera FPGAs while optimizing PCB layout for cost and performance
  • FPGA board design: Introduction to Cadence FPGA System Planner
  • Hitachi: Faster Bring Up with Protium Platform
  • The Best of Both Worlds – Combining Virtual and FPGA-based Prototypes

Technical Brief (1)

  • ASIC Prototyping Simplified Technical Paper

Datasheet (7)

  • Protium S1 FPGA-Based Prototyping Platform
  • Perspec System Verifier Datasheet
  • Protium S1 Single-FPGA Board Datasheet
  • vManager Metric-Driven Signoff Platform Datasheet
  • Palladium Z1 Enterprise Emulation Platform Datasheet
  • Protium FPGA-Based Prototyping Platform Datasheet
  • Allegro FPGA System Planner Datasheet
VIEW ALL
News ReleasesVIEW ALL
  • Cadence Launches Protium X1, the First Scalable, Data Center-Optimized Enterprise Prototyping System for Early Software Development 05/28/2019

  • NVIDIA Deploys the New Cadence Protium X1 Platform to Accelerate Software Development of Large-Capacity GPUs 05/28/2019

  • Cadence Achieves TÜV SÜD’s First Comprehensive “Fit for Purpose - TCL1” Certification in Support of Automotive ISO 26262 Standard 10/11/2017

  • Hiroshima University Research Team Accelerates the Development of a Computer-Aided Medical Diagnosis System with Cadence Tensilica Vision P6 DSP Core and Protium S1 FPGA-Based Prototyping Platform 10/11/2017

  • Amlogic Reduces HW/SW Integration Time for Multimedia SoCs by Two Months Using the Cadence Protium S1 FPGA-Based Prototyping Platform 04/26/2017

Blogs VIEW ALL

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