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Digital Design and Signoff

Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.

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Custom IC / Analog / RF Design

Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.

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System Design and Verification

Cadence® system design and verification solutions, integrated under our Verification Suite, provide the simulation, acceleration, emulation, and management capabilities.

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IP

An open IP platform for you to customize your app-driven SoC design.

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IC Package Design and Analysis

Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.

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  • Cadence Design Solutions certified for TSMC SoIC advanced 3D chip stacking technology Learn More
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System Analysis

Cadence® system analysis solutions provide highly accurate electromagnetic extraction and simulation analysis to ensure your system works under wide-ranging operating conditions.

  • See how to improve electrical-thermal co-simulation with the Celsius™ Thermal Solver Watch Now
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Embedded Software

PCB Design and Analysis

Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.

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  • PRODUCTS
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • Logic Equivalence Checking
        • Innovus Implementation and Floorplanning
        • Functional ECO
        • Low-Power Validation
        • Synthesis
        • Power Analysis
        • Constraints and CDC Signoff
        • Silicon Signoff and Verification
        • Library Characterization
        • Test
        • Flows
      • Custom IC / Analog / RF Design
        • Circuit Design
        • Circuit Simulation
        • Layout Design
        • Layout Verification
        • Library Characterization
        • RF / Microwave Solutions
        • Flows
      • System Design and Verification
        • Debug Analysis
        • Emulation
        • Formal and Static Verification
        • FPGA-Based Prototyping
        • Planning and Management
        • Simulation
        • Software-Driven Verification
        • Verification IP
        • System-Level Verification IP
        • Flows
      • IP
        • Interface IP
        • Denali Memory IP
        • Tensilica Processor IP
        • Analog IP
        • System / Peripherals IP
        • Verification IP
      • IC Package Design and Analysis
        • Cross-Platform Co-Design and Analysis
        • IC Package Design
        • SI/PI Analysis
        • SI/PI Analysis Point Tools
        • Flows
    • SYSTEM INNOVATION
      • System Analysis
        • Electromagnetic Solutions
        • RF / Microwave Design
        • Thermal Solutions
        • System Analysis Resources Hub
      • Embedded Software
      • PCB Design and Analysis
        • Design Authoring
        • PCB Layout
        • Library and Design Data Management
        • Analog/Mixed-Signal Simulation
        • SI/PI Analysis
        • SI/PI Analysis Point Tools
        • What's New in Allegro
        • What's New in Sigrity
        • RF / Microwave Design
        • Flows
        • Advanced PCB Design & Analysis Blog
        • Augmented Reality Lab Tools
    • PERVASIVE INTELLIGENCE
      • AI / Machine Learning
      • AI IP Portfolio
    • CADENCE CLOUD
  • SOLUTIONS
      • INDUSTRIES
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • AI / Machine Learning
      • TECHNOLOGIES
        • 3D-IC Design
        • Advanced Node
        • Arm-Based Solutions
        • Cloud Solutions
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • INDUSTRIES
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • AI / Machine Learning
      • TECHNOLOGIES
        • 3D-IC Design
        • Advanced Node
        • Arm-Based Solutions
        • Cloud Solutions
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • INDUSTRIES
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • AI / Machine Learning
      • TECHNOLOGIES
        • 3D-IC Design
        • Advanced Node
        • Arm-Based Solutions
        • Cloud Solutions
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • INDUSTRIES
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • AI / Machine Learning
      • TECHNOLOGIES
        • 3D-IC Design
        • Advanced Node
        • Arm-Based Solutions
        • Cloud Solutions
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
  • SUPPORT
      • SUPPORT
        • Support Process
        • Online Support
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        • Computing Platform Support
        • Customer Support Contacts
        • Technical Forums
      • TRAINING
        • Custom IC / Analog / RF Design
        • Languages and Methodologies
        • Digital Design and Signoff
        • IC Package
        • PCB Design
        • System Design and Verification
        • Tensilica Processor IP
      • SUPPORT
        • Support Process
        • Online Support
        • Software Downloads
        • Computing Platform Support
        • Customer Support Contacts
        • Technical Forums
      • TRAINING
        • Custom IC / Analog / RF Design
        • Languages and Methodologies
        • Digital Design and Signoff
        • IC Package
        • PCB Design
        • System Design and Verification
        • Tensilica Processor IP
      • SUPPORT
        • Support Process
        • Online Support
        • Software Downloads
        • Computing Platform Support
        • Customer Support Contacts
        • Technical Forums
      • TRAINING
        • Custom IC / Analog / RF Design
        • Languages and Methodologies
        • Digital Design and Signoff
        • IC Package
        • PCB Design
        • System Design and Verification
        • Tensilica Processor IP
      • SUPPORT
        • Support Process
        • Online Support
        • Software Downloads
        • Computing Platform Support
        • Customer Support Contacts
        • Technical Forums
      • TRAINING
        • Custom IC / Analog / RF Design
        • Languages and Methodologies
        • Digital Design and Signoff
        • IC Package
        • PCB Design
        • System Design and Verification
        • Tensilica Processor IP
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ISO 26262 TCL Compliance

Automotive functional safety kits available for download

Automotive Electronics Overview
  • Automotive Solution
  • Advanced Driver Assistance System
  • Automotive Ethernet
  • Infotainment
  • Electronic Control Unit
  • Functional Safety
  • ISO 26262 TCL Compliance

Cadence is the first EDA supplier to achieve comprehensive “Fit for Purpose - Tool Confidence Level 1 (TCL1)” certification enabling automotive semiconductor manufacturers, OEMs and component suppliers to meet stringent ISO 26262 automotive safety requirements. Cadence® tool and flow documentation was evaluated by TÜV SÜD, an internationally accredited independent testing and conformity assessment company, and deemed to be fit for use with ASIL A through ASIL D automotive design projects.

Cadence offers automotive Functional Safety Documentation Kits covering the full spectrum of semiconductor design and verification. The kits satisfy documentation requirements that the automotive component supplier must provide for their tools and flow to achieve ASIL certification. Additionally, the kits reduce the effort required to evaluate tool use cases within each of the supplier’s automotive design projects and help automotive component suppliers avoid the costly efforts of tool-qualification activities.

The automotive Functional Safety Documentation Kits are available through Cadence Online Support and are freely available to all Cadence registered users. Each kit consists of three major components:

  • Safety manual for the specific flow
  • Tool Confidence Analysis (TCA) documents for each tool in the tool chain
  • Compliance report from TÜV SÜD

While the user still has the responsibility to provide assessment documents for each tool in the flow, there is now a defined structure and methodology to do so. The Cadence approach automatically accommodates new tool versions or even new tools in the flow. Cadence will provide updates to the kits as needed, but effectively, the completion of the TÜV SÜD evaluation applies to current and future versions of the Cadence tools and flows.

The Cadence flow documentation that has achieved automotive “Fit for Purpose - TCL1” certification from TÜV SÜD is as follows:

Analog/mixed-signal design, implementation and verification flow: This flow brings transistor-level designs from creation and simulation through physical implementation and verification using the Cadence Virtuoso® ADE Product Suite and the Spectre® Circuit Simulation Platform. The Cadence Virtuoso ADE Verifier provides design engineers with an integrated means to validate the safety specifications against individual circuit specifications for design confidence.

Digital implementation and signoff flow: This flow covers RTL-to-GDSII implementation and signoff. The Cadence Liberate™ Characterization Solution is new to this flow and is incorporated with the 13 other pre-existing tools including the Cadence Innovus™ Implementation System, Genus™ Synthesis Solution, Modus DFT Software Solution, Tempus™ Timing Signoff Solution, Quantus™ Extraction Solution and Voltus™ IC Power Integrity Solution for the implementation and signoff of automotive designs.

PCB design and verification flow: The PCB design flow includes everything from design authoring to simulation to physical realization and verification using the Cadence OrCAD®, PSpice® and Allegro® product suites. The high-performance design entry, simulation and layout editing tools included with these suites provide an integrated environment for design engineers to validate the safety specifications against individual circuit specifications for design confidence.

Additionally, the following flow has been evaluated and confirmed to be compliant with the ISO 26262 standard for automotive safety:

Digital front-end design and verification flow: The flow documentation kit covers specification to RTL design to verification. The front-end digital tools include the Cadence Genus Synthesis Solution and Conformal® Equivalence Checker. Functional and safety verification capabilities are provided by the Cadence Verification Suite, which includes the Cadence JasperGold® Formal Verification Platform, Xcelium™ Parallel Logic Simulator (to be added to the flow documentation in Q4 2017), Palladium® Z1 Enterprise Emulation Platform, Protium™ FPGA-Based Prototyping Platform, vManager™ Metric-Driven Signoff Platform and the Indago™ Debug Platform (to be added to the flow documentation in Q4 2017). 

  • Digital Design and Verification Tools

    • SimVision Debug
    • vManager Verification Management
    • JasperGold Formal Verification Platform
    • Palladium Z1 Enterprise Emulation Platform
    • Protium FPGA-Based Prototyping Platform
    • Conformal Overview
    • Genus Synthesis Solution
  • Analog Design, Verification, and Implementation Tools

    • Quantus Extraction Solution
    • SimVision Debug
    • Spectre Accelerated Parallel Simulator
    • Spectre eXtensive Partitioning Simulator (XPS)
    • Spectre RF Option
    • Virtuoso ADE Product Suite
    • Virtuoso ADE Verifier
    • Virtuoso Schematic Editor
    • Spectre AMS Designer
  • Digital Implementation and Signoff

    • Stratus High-Level Synthesis
    • Genus Synthesis Solution
    • Cadence Modus DFT Software Solution
    • Innovus Implementation System
    • Physical Verification System
    • Conformal Equivalence Checker
    • Joules RTL Power Solution
    • Quantus Extraction Solution
    • Tempus Timing Signoff Solution
    • Voltus IC Power Integrity Solution
    • Voltus-Fi Custom Power Integrity Solution
    • Litho Physical Analyzer
    • CMP Predictor
    • Liberate Characterization Solution
  • PCB Design and Verification

    • Allegro Design Entry Capture/Capture CIS
    • Allegro Design Authoring
    • Allegro PCB Designer
    • Allegro PSpice System Designer

Hans Adlkofer, Vice President and Head of Automotive Systems Group, at Infineon Technologies AG explains how Infineon leverages Cadence products for Automotive Chip design to enable smart and safe mixed-signal devices.

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News ReleasesVIEW ALL
  • Cadence Tensilica Product Development Process and Software Products Certified for ISO 26262 ASIL D Compliance for Automotive Applications 02/28/2019

  • Cadence Automotive Solution for Safety Verification Used by ROHM to Achieve ISO 26262 ASIL D Certification 07/12/2018

  • Cadence Debuts Industry’s First Analog IC Design-for-Reliability Solution 05/08/2018

  • Cadence Boosts Vision and AI Performance with New Tensilica Vision Q6 DSP IP 04/11/2018

  • Cadence Achieves TÜV SÜD’s First Comprehensive “Fit for Purpose - TCL1” Certification in Support of Automotive ISO 26262 Standard 10/11/2017

Blogs VIEW ALL

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