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Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.

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An open IP platform for you to customize your app-driven SoC design.

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Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.

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  • Products
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Genus Synthesis Solution
          • Conformal Smart LEC
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Virtuoso RF Solution
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus IC Power Integrity Solution
          • RESOURCES
          • Flows
      • System Design and Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Emulation
          • Formal and Static Verification
          • FPGA-Based Prototyping
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • JasperGold Formal Verification Platform
          • Xcelium Logic Simulation
          • Palladium Z1 Enterprise Emulation Platform
          • Protium X1 Enterprise Prototyping Platform
          • System VIP
          • RESOURCES
          • Flows
      • IP
        • PRODUCT CATEGORIES
          • Interface IP
          • Denali Memory IP
          • Tensilica Processor IP
          • Analog IP
          • System / Peripherals IP
          • Verification IP
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
      • System Analysis
        • PRODUCT CATEGORIES
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Sigrity Advanced SI
          • Sigrity Advanced PI
          • RESOURCES
          • System Analysis Resources Hub
      • Embedded Software
      • PCB Design and Analysis
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • RESOURCES
          • What's New in Allegro
          • What's New in Sigrity
          • Advanced PCB Design & Analysis Resources Hub
          • Flows
    • PERVASIVE INTELLIGENCE
      • AI / Machine Learning
      • AI IP Portfolio
    • CADENCE CLOUD
    • VIEW ALL PRODUCTS
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        • Low Power
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Verification IP for Arm AMBA Protocols

Broad, proven solution addresses wide range of SoC verification needs

  • Arm-Based Solutions
  • Verification Solution for Arm-Based Designs
  • Arm-Based SoC Implementation
  • IoT Reference Platform
  • Verification IP for Arm AMBA Protocols

Key Benefits

  • Comprehensive solution improves SoC quality and performance
  • Dependable results enable predictable verification schedules
  • Consistent and easy-to-use products boost productivity

The most time-consuming aspect of system-on-chip (SoC) functional verification is often the creation of a testbench that accurately stimulates and responds to the interfaces on the design under test. Since a typical SoC contains dozens of standard interfaces and multiple, layered interconnect fabrics, Verification IP (VIP) provides a huge benefit by modeling all those interfaces as components that can be plugged into a testbench and simulated along with the design under test. This offloads a substantial amount of work from the verification engineer, saving time and improving product quality.

Performance Verification

Many SoCs now employ sophisticated interconnect fabric IP to link multiple processor cores, caches, memories, and dozens of other IP blocks. These interconnect fabrics are enabling new generations of low-power servers and high-performance mobile devices. However, the added complexity of these interconnect fabrics requires VIP solutions to verify data integrity and SoC performance in addition to protocol compliance.

Cadence® Verification IP for Arm® AMBA® protocols is a complete SoC verification solution providing:

  • Protocol compliance with simulation VIP and assertion-based VIP
  • Data integrity analysis with Interconnect Validator
  • Performance verification with Interconnect Workbench
  • Simplified debugging with Indago Protocol Debug App
  • Hardware/software verification with accelerated VIP

Customer Satisfaction

Cadence VIP for AMBA protocols has been expanding and improving over more than 10 years. Hundreds of customers have verified thousands of AMBA-based designs with Cadence VIP.

Verification IP Customer Satisfaction

Arm AMBA Protocol Family Overview

  • Related Products

    • Verification Solution for Arm-Based Designs
    • Arm-Based SoC Implementation
    • IoT Reference Platform
Videos

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Tackling 16nm Challenges for Arm Cortex-A72 Processor

Arm AMBA Protocol Overview

ARM and Cadence Partner to Facilitate Mixed-Signal Designs

Improving Performance of SoCs with Interconnect Workbench and CoreLink System IP

News ReleasesVIEW ALL
  • Arm, Cadence and Xilinx Introduce First Arm Neoverse System Development Platform for Next-Generation Cloud-to-Edge Infrastructure, Implemented on TSMC 7nm Process Technology 03/12/2019

  • Cadence and ARM Deliver an IP Reference System for Internet of Things Applications 11/09/2015

  • Cadence Announces Verification IP for ARM AMBA 5 AHB5 11/09/2015

  • Cadence and ARM Announce Strategic IP Interoperability Agreement 03/17/2015

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