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Digital Design and Signoff

Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.

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  • China - 简体中文
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  • Products
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Genus Synthesis Solution
          • Conformal Smart LEC
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Virtuoso RF Solution
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus IC Power Integrity Solution
          • RESOURCES
          • Flows
      • System Design and Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Emulation
          • Formal and Static Verification
          • FPGA-Based Prototyping
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • JasperGold Formal Verification Platform
          • Xcelium Logic Simulation
          • Palladium Z1 Enterprise Emulation Platform
          • Protium X1 Enterprise Prototyping Platform
          • System VIP
          • RESOURCES
          • Flows
      • IP
        • PRODUCT CATEGORIES
          • Interface IP
          • Denali Memory IP
          • Tensilica Processor IP
          • Analog IP
          • System / Peripherals IP
          • Verification IP
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
      • System Analysis
        • PRODUCT CATEGORIES
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Sigrity Advanced SI
          • Sigrity Advanced PI
          • RESOURCES
          • System Analysis Resources Hub
      • Embedded Software
      • PCB Design and Analysis
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • RESOURCES
          • What's New in Allegro
          • What's New in Sigrity
          • Advanced PCB Design & Analysis Resources Hub
          • Flows
    • PERVASIVE INTELLIGENCE
      • AI / Machine Learning
      • AI IP Portfolio
    • CADENCE CLOUD
    • VIEW ALL PRODUCTS
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        • Cloud Solutions
        • Low Power
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        • RF / Microwave
      • Industries
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        • AI / Machine Learning
      • Technologies
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Arm-Based SoC Implementation

Digital design flows optimized for Arm-based applications

  • Arm-Based Solutions
  • Verification Solution for Arm-Based Designs
  • Arm-Based SoC Implementation
  • IoT Reference Platform
  • Verification IP for Arm AMBA Protocols

Key Benefits

  • Lower risk to develop Arm core-based SoCs
  • Easy to use for higher productivity
  • Shorter timeframe needed to meet PPA targets
  • PPA push technology and expertise to help with last-mile closure 

Arm works with EDA vendors to develop EDA reference flows. Working closely with Arm, Cadence has optimized our full-flow digital solution for Arm®-based designs. Using the resulting digital implementation reference flows, you can efficiently implement your Arm core-based systems on chip (SoCs) and reach your power, performance, and area (PPA) targets much faster versus using generic EDA reference flows.

Arm utilizes Cadence® tools to develop its IP.  We have early access to Arm cores, so we can tune our tool algorithms, features, and options, and can optimize our flow before the official release of the Arm cores. All of this leads to an added PPA and turnaround time (TAT) boost on top of generic EDA reference flow results.

Flows are available for many Arm Cortex®-A, Cortex-R, Cortex-M, and NeoverseTM cores, multimedia products (GPUs, display controllers, video controllers), and interconnect cores. You’ll get an optimized starting point of scripts, floorplans, and documentation for these CPU and GPU configurations as well as for popular foundry process technologies, including FinFET and other advanced nodes.  

Fast Turnaround with Predictable PPA

As you implement the Arm cores on Cadence’s RTL-to-signoff flow, we bring in experienced R&D staff and product engineers who have worked closely with Arm to build reference flows. These technical experts also have experience helping with the PPA push on several tapeouts worldwide on advanced Arm designs, spanning a range of technologies from 40nm to 10nm and below.

Cadence’s digital implementation reference flows are supported by our early collaboration with Arm. With our reference flows, you get design techniques, from RTL to GDSII, for Arm processors, reducing time to silicon with predictable PPA results. Contact your Cadence Sales representative for more information. The flows are also optimized with Arm POP™ IP core-hardening acceleration technology. Using these flows, you’ll be equipped to efficiently produce optimized SoCs based on Arm big.LITTLE™ processing systems.

Optimizing for Low Power

Cadence provides a comprehensive solution to design, verify, and optimize power consumption on Arm-based SoCs:

  • Functional verification of all the power modes of Arm cores is accelerated using the Xcelium simulator and Palladium® Z1 emulation platform
  • Joules™ RTL Power Solution helps to accurately estimate power at an early stage of the design and to identify peak power under realistic system usage scenarios
  • The Genus™ Synthesis Solution and the Innovus™ Implementation System help to concurrently optimize leakage and dynamic power while simultaneously maximizing performance and minimizing area
  • Conformal® Low Power is the industry-leading low-power formal tool that is routinely used to validate Arm-based SoC designs
  • Cadence signoff tools, including Tempus™ Timing Signoff Solution, Quantus™ Extraction Solution, and Voltus™ IC Power Integrity Solution, help accelerate signoff, so you can tape out Arm-based SoCs with confidence
  • All tools in the low-power flow support power intent for Arm-based SoCs described in industry-standard CPF and IEEE 1801 power formats
  • Related Products

    • Genus Synthesis Solution
    • Joules RTL Power Solution
    • Cadence Modus DFT Software Solution
    • Quantus Extraction Solution
    • Tempus Timing Signoff Solution
    • Voltus IC Power Integrity Solution
    • Physical Verification System
  • Rapid Adoption Kits for ARM-Based Designs

    • Rapid Adoption Kits (RAKs) for Arm-Based Designs
Videos

2.2 GHz Performance on 28nm ARM Dual-Core Cortex-A9 Processor

Lowering Leakage Power in ARM Cortex-A17 Processor-based SoCs at GLOBALFOUNDRIES

Tackling 16nm Challenges for Arm Cortex-A72 Processor

Arm AMBA Protocol Overview

ARM and Cadence Partner to Facilitate Mixed-Signal Designs

Improving Performance of SoCs with Interconnect Workbench and CoreLink System IP

News ReleasesVIEW ALL
  • Cadence Collaborates with Arm and Samsung Foundry on Delivery of 5LPE Flow for Mission-Critical Applications Using Next-Generation “Hercules” CPU 10/08/2019

  • Arm, Cadence and Xilinx Introduce First Arm Neoverse System Development Platform for Next-Generation Cloud-to-Edge Infrastructure, Implemented on TSMC 7nm Process Technology 03/12/2019

  • Cadence Tools and IP Optimized for New Arm Neoverse N1 Platform to Advance the Cloud-to-Edge Infrastructure Market 02/20/2019

  • Cadence Full-Flow Digital and Signoff Tools and Verification Suite Provide Optimal Results for 7nm Arm Cortex-A76 CPU Designs 05/31/2018

  • Cadence Full-Flow Digital and Signoff and Verification Suite Optimized to Support Arm Cortex-A75 and Cortex-A55 CPUs and Arm Mali-G72 GPU 08/07/2017

Blogs VIEW ALL
Customers

We partnered closely with Cadence to utilize the Innovus Implementation System during the development of our ARM Cortex-A72 processor. This demonstrated a 5X runtime improvement over previous projects and will deliver more than 2.6GHz performance within our area target.

Noel Hurley, General Manager, CPU Group, ARM

Read More or View All Customers

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