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  • Products

    • Products

      Cadence.AI

      • Millennium Platform

        AI-driven digital twin supercomputer

      • Cadence Cerebrus AI Studio

        Multi-block, multi-user SoC design platform

      • Optimality Intelligent System Explorer

        AI-driven Multiphysics analysis

      • Verisium Verification Platform

        AI-driven verification platform

      • Allegro X AI

        AI-driven PCB Design

      • Tensilica AI Platform

        On-device AI IP

    • Products

      IC Design & Verification

      • Virtuoso Studio

        Analog and custom IC design

      • Spectre Simulation

        Analog and mixed-signal SoC verification

      • Innovus+ Platform

        Synthesis and implementation for advanced nodes

      • Xcelium Logic Simulation

        IP and SoC design verification

      • Silicon Solutions

        Protocol IP and Compute IP, including Tensilica IP

      • Palladium and Protium

        Emulation and prototyping platforms

    • Products

      System Design & Analysis

      • Allegro X Design Platform

        System and PCB design platform

      • Allegro X Adv Package Designer Platform

        IC packaging design and analysis platform

      • Sigrity X Platform

        Signal and power integrity analysis platform

      • AWR Design Environment Platform

        RF and microwave development platform

      • Cadence Reality Digital Twin Platform

        Data center design and management platform

      • Fidelity CFD Platform

        Computational fluid dynamics platform

    • All Analog IC Design Products
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    • 3D-IC Design

    • Advanced Node

    • Arm-Based Solutions

    • Cloud Solutions

    • Computational Fluid Dynamics

    • Functional Safety

    • Low Power

    • Mixed-signal

    • Molecular Simulation

    • Multiphysics System Analysis

    • Photonics

    • RF / Microwave

    Designed with Cadence See how our customers create innovative products with Cadence
    Explore Cadence Cloud Now Explore Cadence Cloud Now
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Free Trials

Arm-Based SoC Implementation

Digital design flows optimized for Arm-based applications

Watch Arm Neoverse Video Watch Ampere Video
  • Arm-Based Solutions
  • Verification Solution for Arm-Based Designs
  • Arm-Based SoC Implementation
  • Verification IP for Arm AMBA Protocols
  • Arm SystemReady Compliance

Key Benefits

  • Lower risk to develop Arm core-based SoCs
  • Easy to use for higher productivity
  • Shorter timeframe needed to meet PPA targets
  • PPA push technology and expertise to help with last-mile closure 

Arm works with EDA vendors to develop EDA reference flows. Working closely with Arm, Cadence has optimized our full-flow digital solution for Arm®-based designs. Using the resulting digital implementation reference flows, you can efficiently implement your Arm core-based systems on chip (SoCs) and reach your power, performance, and area (PPA) targets much faster versus using generic EDA reference flows.

Arm utilizes Cadence® tools to develop its IP.  We have early access to Arm cores, so we can tune our tool algorithms, features, and options, and can optimize our flow before the official release of the Arm cores. All of this leads to an added PPA and turnaround time (TAT) boost on top of generic EDA reference flow results.

Flows are available for many Arm Cortex®-A, Cortex-R, Cortex-M, and Neoverse cores, multimedia products (GPUs, display controllers, video controllers), and interconnect cores. You’ll get an optimized starting point of scripts, floorplans, and documentation for these CPU and GPU configurations as well as for popular foundry process technologies, including FinFET and other advanced nodes.  

Fast Turnaround with Predictable PPA

As you implement the Arm cores on Cadence’s RTL-to-signoff flow, we bring in experienced R&D staff and product engineers who have worked closely with Arm to build reference flows. These technical experts also have experience helping with the PPA push on several tapeouts worldwide on advanced Arm designs, spanning a range of technologies from 40nm to 10nm and below.

Cadence’s digital implementation reference flows are supported by our early collaboration with Arm. With our reference flows, you get design techniques, from RTL to GDSII, for Arm processors, reducing time to silicon with predictable PPA results. Contact your Cadence Sales representative for more information. The flows are also optimized with Arm POP IP core-hardening acceleration technology. Using these flows, you’ll be equipped to efficiently produce optimized SoCs based on Arm big.LITTLE processing systems.

Optimizing for Low Power

Cadence provides a comprehensive solution to design, verify, and optimize power consumption on Arm-based SoCs:

  • Functional verification of all the power modes of Arm cores is accelerated using the Xcelium simulator and Palladium® Z1 emulation platform
  • Joules RTL Power Solution helps to accurately estimate power at an early stage of the design and to identify peak power under realistic system usage scenarios
  • The Genus Synthesis Solution and the Innovus Implementation System help to concurrently optimize leakage and dynamic power while simultaneously maximizing performance and minimizing area
  • Conformal® Low Power is the industry-leading low-power formal tool that is routinely used to validate Arm-based SoC designs
  • Cadence signoff tools, including Tempus Timing Signoff Solution, Quantus Extraction Solution, and Voltus IC Power Integrity Solution, help accelerate signoff, so you can tape out Arm-based SoCs with confidence
  • All tools in the low-power flow support power intent for Arm-based SoCs described in industry-standard CPF and IEEE 1801 power formats
  • Related Products
    • Genus Synthesis Solution
    • Joules RTL Power Solution
    • Quantus Extraction Solution
    • Tempus Timing Solution
    • Voltus IC Power Integrity Solution
    • Physical Verification System
  • Rapid Adoption Kits for ARM-Based Designs
    • Rapid Adoption Kits (RAKs) for Arm-Based Designs
Videos

How We Push Largest 5nm High-Performance Arm Core to 4GHz Frequency

Cadence and Arm Collaborate to Reduce Automotive Arm-Based SoC Time-to-Market

Better PPA with Innovus Mixed Placer Technology – Gigaplace XL

Cadence collaborates with Arm to optimize Neoverse implementation

Cadence and Arm Collaboration to Speed Server Development

2.2 GHz Performance on 28nm ARM Dual-Core Cortex-A9 Processor

Lowering Leakage Power in ARM Cortex-A17 Processor-based SoCs at GLOBALFOUNDRIES

Tackling 16nm Challenges for Arm Cortex-A72 Processor

Whiteboard Wednesdays - ARM AMBA Protocol Usage

News ReleasesVIEW ALL
  • Cadence Collaborates with Arm to Accelerate Mobile Device Silicon Success with New Arm Total Compute Solutions 05/28/2023

  • Cadence Expands Collaboration with Arm to Accelerate Mobile Device Silicon Success 06/28/2022

  • Cadence Collaboration with Arm Enables Customers to Successfully Tape out Next-Generation Arm Mobile Designs 05/25/2021

  • Cadence Collaborates with Arm to Accelerate Hyperscale Computing and 5G Communications SoC Development 04/27/2021

  • Cadence Collaborates with Arm and Samsung Foundry on Delivery of 5LPE Flow for Mission-Critical Applications Using Next-Generation “Hercules” CPU 10/08/2019

Blogs VIEW ALL
Customers

We partnered closely with Cadence to utilize the Innovus Implementation System during the development of our ARM Cortex-A72 processor. This demonstrated a 5X runtime improvement over previous projects and will deliver more than 2.6GHz performance within our area target.

Noel Hurley, General Manager, CPU Group, ARM

Read More or View All Customers
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