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Digital Design and Signoff

Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.

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Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.

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  • Products
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Genus Synthesis Solution
          • Conformal Smart LEC
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Virtuoso RF Solution
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus IC Power Integrity Solution
          • RESOURCES
          • Flows
      • System Design and Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Emulation
          • Formal and Static Verification
          • FPGA-Based Prototyping
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • JasperGold Formal Verification Platform
          • Xcelium Logic Simulation
          • Palladium Z1 Enterprise Emulation Platform
          • Protium X1 Enterprise Prototyping Platform
          • System VIP
          • RESOURCES
          • Flows
      • IP
        • PRODUCT CATEGORIES
          • Interface IP
          • Denali Memory IP
          • Tensilica Processor IP
          • Analog IP
          • System / Peripherals IP
          • Verification IP
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
      • System Analysis
        • PRODUCT CATEGORIES
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Sigrity Advanced SI
          • Sigrity Advanced PI
          • RESOURCES
          • System Analysis Resources Hub
      • Embedded Software
      • PCB Design and Analysis
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • RESOURCES
          • What's New in Allegro
          • What's New in Sigrity
          • Advanced PCB Design & Analysis Resources Hub
          • Flows
    • PERVASIVE INTELLIGENCE
      • AI / Machine Learning
      • AI IP Portfolio
    • CADENCE CLOUD
    • VIEW ALL PRODUCTS
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        • Automotive
        • AI / Machine Learning
      • Technologies
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Digital Advanced Node

Best quality of results for challenging FinFET designs  

  • Advanced-Node Solutions
  • Custom/Analog Advanced Node
  • Digital Advanced Node

Key Benefits

  • Massively parallel technology facilitates the handling of the large data size and complexity of advanced nodes
  • Smart algorithms implemented over integrated engines provide best PPA benefits
  • Comprehensive full-flow integrated digital toolset for design creation, implementation, and signoff enabling faster convergence and design closure for advanced nodes
Meeting the challenge of advanced nodes

Advanced FinFET devices and planar devices with FD-SOI technology improve power, performance, and area (PPA), but create additional design challenges. Cadence developed its revolutionary full-flow digital toolset to address these design challenges at the design creation, implementation, and signoff stages. Here are just some of the issues designers can run into with these transistors:

  • Leakage power is reduced, but now dynamic power becomes more significant
  • Double patterning is used to enhance feature density as single-pass lithography falls short
  • Placement and optimization must consider new advanced-node base-layer constraints
  • Larger port capacitance of devices adds to total capacitance on wires
  • Designs operate at lower voltages, so design flows need to handle lower vdds
  • Electromigration and IR become a bigger concern with increased drive strength and high-resistance wires
  • On-chip variation plays a bigger role and must be mitigated through correct statistical algorithms
  • Transistor self-heating effects can affect signal RMS current

The Cadence® Full-Flow Digital Implementation and Signoff tools can handle and support all the special requirements of today’s FinFET and advanced-node FD-SOI designs. These tools prevent and correct harmful lithography hotspots, random defects, on-chip variation, and variation due to chemical-mechanical polishing. Using rule- and model-based in-design analysis (pre-qualified and closely related with foundry process simulation), the Cadence Innovus™ Implementation System minimizes risk upfront and prevents unexpected design re-spins and late-stage iterations.

Designing for double patterning and beyond

As design is moving below 20nm, fabs are employing double patterning to enhance the feature density, as single lithographic exposure generally is not enough to provide sufficient resolution. At 16nm and 14nm, shapes are so close that single-pass lithography has many interference effects, and multi-pass lithography is required. With two-pass lithography, each pass prints one mask of double-pitch wires. When both passes are complete, a single layout with minimum spacing wires is created.

At 7nm, explicit full-flow coloring is required during design. RC characteristics are color dependent, even on the same metal layer. Older software for IC design can’t handle the double patterning or explicit coloring required. But Cadence’s implementation and signoff tools were designed, from the start, to help designers deal with these and other effects of very small geometries.

Digital toolset optimized for advanced nodes

Cadence completely re-invented its digital tool set for advanced nodes, starting with a unified software architecture. This integrated digital architecture is based on a foundation of core common engines and full-flow optimizations. When new features are added in one place, multiple applications benefit. This enables smarter software, with fewer bugs, rapid feature deployment for newer nodes, accurate early prediction, and convergent correlation.

Unified Software Architecture

 

The Cadence full-flow digital solution offers massive parallelization that works to your advantage. Other point-tool-oriented flows create inefficiencies due to parallelism, with multiple bottlenecks between synthesis and implementation and between optimization and signoff. By using full-flow parallelism, Cadence avoids those bottlenecks and provides a much faster turnaround time.

Full Flow Parallelism

 

Design creation starts with the Cadence Genus™ Synthesis Solution, which utilizes an early physical approach for placement, congestion predictability, layer assignment, layer-aware buffering, RTL optimization, and considerations for area, timing, and power. With a unified placement engine, global routing engine, delay calculation, and parasitic extraction, the Genus solution prepares your design for implementation.

The Cadence Innovus Implementation System provides full support for coloring, double patterning and a unique via pillar methodology for high-performance computing requirements. The GigaPlace™ Engine, which uses a look-ahead placement approach, includes features that are useful for advanced-node designs, including activity-driven placement, slack- and power-driven placement, pin-access-aware placement, and IR-driven placement. The NanoRoute™ Advanced Digital Router is optimized for highly complex designs that include multiple CPUs and other complex logic. The GigaOpt™ Optimizer considers advanced-node characteristics such as correct layer selection for optimal buffering. Layer-aware route-driven optimization technology provides huge improvements in timing closure.

Signoff speed and efficiency

Over the past few years, Cadence has introduced totally revamped tools to facilitate advanced-node signoff. These tools are all integrated, and include our Quantus™ Extraction Solution; the Liberate™ Characterization portfolio providing robust solutions for the characterization, variation modeling, and validation of foundation IP, from standard cells, I/Os, and complex multi-bit cells to memories and mixed-signal blocks; the Tempus™ Timing Signoff Solution for signoff static timing analysis; the Voltus™ IC Power Integrity Solution; and the Pegasus™ Verification System for massively parallel physical signoff and DRC, LVS, and DFM.

These sophisticated signoff tools are fully integrated with the Cadence synthesis and implementation tool sets to provide designers with one integrated tool flow for the entire design process.

In summary, Cadence’s Advanced-Node Digital Implementation Solution with massive parallelization, shared engines infrastructure, and in-design signoff offers a unique and comprehensive solution for designing breakthrough technology using FinFETs or FD-SOI technology at advanced nodes.

Reality Is Not Linear

The changing landscape
of physical design

HEAR THE INTERVIEW
  • Related Products

    • Innovus Implementation System
    • Quantus Extraction Solution
    • Tempus Timing Signoff Solution
    • Voltus IC Power Integrity Solution
    • Physical Verification System
    • Genus Synthesis Solution
    • Cadence Modus DFT Software Solution
    • Liberate Trio Characterization Suite
    • Liberate MX Memory Characterization
    • Liberate AMS Mixed-Signal Characterization
    • Liberate LV Library Validation Solution
    • Liberate Variety Statistical Characterization
    • Spectre Accelerated Parallel Simulator
    • Spectre eXtensive Partitioning Simulator (XPS)
Videos

Offering Leading Edge Total Solutions - GLOBALFOUNDRIES Design Ready 14nm Eco System

Samsung Foundry 14LPP: The Continual Thrust in FinFET Leadership

Physical Design Flow Challenges at 28nm on Multi-Million Gate Blocks

Physical Design Analytics and DFM Enablement for sub-14nm Technology Nodes

Silicon Signoff and Verification - 16nm FinFET Challenges and Features

News ReleasesVIEW ALL
  • Cadence Completes Acquisition of NUMECA 02/24/2021

  • Cadence's Lip-Bu Tan to Present at Morgan Stanley Conference 02/23/2021

  • Cadence Reports Fourth Quarter and Fiscal Year 2020 Financial Results 02/22/2021

  • Cadence Announces $5M Endowment at Massachusetts Institute of Technology 02/02/2021

  • Cadence to Acquire NUMECA to Expand System Analysis Capabilities with Computational Fluid Dynamics 01/20/2021

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