Overview

Preferred Partner for Every New Process Node Down to 2nm

What makes designing at 22nm and below advanced nodes unique is the deep, complex interdependency of manufacturing and variability, on top of increasing power and performance specifications. The concerns include the following:

  • Multiple-patterning technology (MPT) and color-aware physical design, including double, triple, quadruple, and penta-patterning
  • Layout-dependent effects (LDE) and density-gradient effects (DGE), in which the layout context—what is placed near a device—can impact device performance by as much as 30%
  • Sophisticated color-aware custom routing
  • Exponentially increasing physical design rules
  • Device variation and sensitivity

Key Benefits

Improved Design Productivity at Advanced Nodes to Meet Your Time-to-Market Goals

Increase Silicon Quality

Scale to thousands of simulations to meet the most aggressive advanced-node process challenges

Productivity Through Automation

New design methodologies and targeted automation techniques enhance productivity by up to 10X versus traditional design tools and flows

Reuse Experience Through Design Migration

Jumpstart new designs with design and layout migration from one process node to another

Avoid Costly Respins

Close collaboration with leading foundries provides capabilities to predict and manage process variability up front in the design flow

Proven Solution

Certified by all major foundries for advanced technologies from FinFETs to GAAFETs

Features

Industry-Leading Methodologies to Overcome Unique Design Challenges of Advanced-Node Processes

  • Improved multi-threaded core editing performance for scalability
  • Schematic PCell caching for faster netlisting of large, stacked transistors
  • Multi-gridded assisted placement for structured layout methodology
  • Abstracted matched device arrays using module generators (Modgens)
  • Simulation-driven interactive track-based wire creation with automatic coloring support
  • Integrated placement and routing methodology for fully automated custom layout creation with advanced custom/analog constraint support
  • Signoff quality in-design DRC
  • In-design parasitic and EM-IR verification with constraint checking
  • Enhanced custom design and layout migration solution to migrate from one advanced-process node to another

Technologies

Custom Design Migration

Integrated Place and Route

Resources

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News

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Cadence Digital, Custom/Analog Design Flows Certified and Design IP Available for Intel 16 FinFET Process

  • 11 Jul 2023
  • News Release

Cadence Digital and Custom/Analog Design Flows Certified for TSMC’s Latest N3E and N2 Process Technologies

  • 26 Apr 2023
  • News Release

Cadence Custom Design Migration Flow Accelerates Adoption of TSMC N3E and N2 Process Technologies

  • 25 Apr 2023
  • News Release
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Blogs

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Training and Support

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Training

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Online Support

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Technical Forums

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