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  • Products
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Genus Synthesis Solution
          • Conformal Smart LEC
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
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          • Spectre X Simulator
          • Virtuoso RF Solution
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus IC Power Integrity Solution
          • RESOURCES
          • Flows
      • System Design and Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Emulation
          • Formal and Static Verification
          • FPGA-Based Prototyping
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • JasperGold Formal Verification Platform
          • Xcelium Logic Simulation
          • Palladium Z1 Enterprise Emulation Platform
          • Protium X1 Enterprise Prototyping Platform
          • System VIP
          • RESOURCES
          • Flows
      • IP
        • PRODUCT CATEGORIES
          • Interface IP
          • Denali Memory IP
          • Tensilica Processor IP
          • Analog IP
          • System / Peripherals IP
          • Verification IP
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
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          • RF / Microwave Design
          • Thermal Solutions
        • FEATURED PRODUCTS
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          • Celsius Thermal Solver
          • Sigrity Advanced SI
          • Sigrity Advanced PI
          • RESOURCES
          • System Analysis Resources Hub
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        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
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          • Augmented Reality Lab Tools
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          • Allegro Package Designer Plus
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5G Radiohead

  • 5G Systems and Subsystems
  • 5G Handset
  • 5G Radiohead
  • 5G Baseband and Edge Computing
  • 5G Fronthaul and Backhaul

5G combines existing spectrum and new millimeter wave (mmWave), and it’s this higher frequency mmWave that provides both benefits and design challenges for 5G. At these frequencies, patch antenna size is much reduced for radioheads, to the size of a fingernail, but conversely, signal attenuation is high, so antennas are placed in 2D arrays. This enables beamforming to concentrate and direct the signal energy over greater distances.

An array of patch antenna the size of your palm may cover one side of a radiohead PCB module, with the other side populated with the RFICs to drive them. Such compact high-frequency modules demand a design environment that blends design for electromagnetic and radio frequency, and the co-design of IC, package, and module with GaAs, GaN, and Si technologies. To meet this fundamental 5G design need, Cadence created the Virtuoso® RF Solution, so engineers can account for all these concerns within an integrated environment that incorporates multiple EM solvers.

RFICs for 5G will necessarily contain many digital functions, such as decimation, clipping, and particularly digital pre-distortion; essential for power amplifier linearity and the uncompressed constellation diagrams demanded by the high-performance 5G modulation scheme 1024-QAM. To enable this type of digitized RFIC design, Cadence provides Virtuoso Digital Implementation, which works with the Virtuoso RF Solution through a common OpenAccess database, Spectre® AMS Designer and Spectre eXtensive Partitioning Simulator (XPS), all elements of the Cadence Mixed-Signal Solutions.

System-level design and detailed evaluation of digital pre-distortion algorithms is achieved through the Cadence partnership with MathWorks, using MathWorks Simulink and Cadence Spectre RF Option together to design, integrate, and validate the algorithm with the RF chain.

Narrowly formed beams create a need for many more radioheads, with line-of-sight inside and outside of buildings and on masts, and here small form-factor and low cost is key, as well as temperature ranges from -40℃ to 125℃. Using the Allegro® PCB Designer RF Option for PCB design, with Cadence connections to mechanical CAD partners Dassault Systemes, PTC, and Siemens, means the radiohead PCB and housing can be co-designed for optimal performance, size, and cost.

With so many antennas to drive for massive multiple input/multiple output (MIMO), power reduction is key. With a wide variety of digital baseband, RF, and hybrid beamforming architectures to help meet this goal, the Cadence Low-Power Solution can help meet the low-power objectives for radiohead design.

 

Tell Me More About 5G

Learn about the design of a mixed-signal RF chain using Mathworks and Cadence tools in combination.

  • Related Products

    • Virtuoso RF Solution
    • Mixed-Signal Solutions
    • Spectre RF Option
    • Allegro PCB Designer
    • Spectre eXtensive Partitioning Simulator (XPS)
    • Spectre AMS Designer
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