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  • China - 简体中文
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  • Products
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Integrity 3D-IC Platform
          • Cadence Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Voltus IC Power Integrity Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Spectre FX Simulator
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus-Fi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Virtual Prototyping
          • Emulation and Prototyping
          • Static and Formal Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
      • IP
        • PRODUCT CATEGORIES
          • 112G/56G SerDes
          • Chiplet and D2D
          • Denali Memory Interface and Storage IP
          • Interface IP
          • PCIe and CXL
          • Tensilica Processor IP
        • RESOURCES
          • Discover PCIe
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
      • Multiphysics System Analysis
        • PRODUCT CATEGORIES
          • Computational Fluid Dynamics
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Signal and Power Integrity
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Solver Cloud
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Fidelity CFD
          • Sigrity Advanced SI
          • Celsius Advanced PTI
          • RESOURCES
          • System Analysis Center
          • System Analysis Resources Hub
          • AWR Free Trial
      • Embedded Software
      • PCB Design and Analysis
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • Allegro X Design Platform
          • RESOURCES
          • What's New in Allegro
          • Advanced PCB Design & Analysis Resources Hub
          • Flows
      • Computational Fluid Dynamics
    • PERVASIVE INTELLIGENCE
      • AI / Machine Learning
      • AI IP Portfolio
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        • 5G Systems and Subsystems
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        • Advanced Node
        • AI / Machine Learning
        • Arm-Based Solutions
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        • Functional Safety
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • Industries
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • Hyperscale Computing
      • Technologies
        • 3D-IC Design
        • Advanced Node
        • AI / Machine Learning
        • Arm-Based Solutions
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        • Low Power
        • Mixed Signal
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5G Handset

  • 5G Systems and Subsystems
  • 5G Handset
  • 5G Radiohead
  • 5G Baseband and Edge Computing
  • 5G Fronthaul and Backhaul

5G RF module designs for handsets can exploit the very large bandwidth offered by millimeter wave (mmWave), but must also meet significant challenges in linearity, power, and heat necessary to be successful in the handset market. You face intense pressure on form factor with tight integration of RFICs, baseband, power management, discretes, and multiple-input/multiple-output (MIMO) antenna arrays with advanced packaging. And as more bands are added and repurposed for 5G over the next five years or so, there’s an evolution opportunity to improve the modules further, for performance, power, and area (PPA).

RF Module Designs

To achieve such low-power multi-standard modules in such densely packed form factors at such high frequencies takes a new class of RF design tool. For this, we created the Cadence® Virtuoso® RF Solution for co-design of RFIC, package, and module substrates using a free mix of GaAs, GaN, and Si transceiver technologies, developed with the Cadence AWR Design Environment platform. 

For initial 5G rollout utilizing existing 4G infrastructure, i.e., 5G NSA (non-standalone), handset data will be 5G and control will be 4G. Potential harmonic interference between the two standards must be addressed through careful filter and power amplifier (PA) design. 5G PA design needs integrated envelope tracking, average power tracking, and back off to maximize handset battery life and the linearity demanded by dense 5G modulation schemes. To address this, the Spectre® X Simulator provides fast simulation speeds and golden accuracy with up to 10X performance improvement.

The Cadence Low-Power Solution ensures power minimization for handset 5G module IC design. This comprehensive solution encompasses architecture optimization, power estimation and analysis, functional verification, implementation and signoff, and IP for digital and mixed-signal designs at both the chip and system level.

Designers can conduct thermal analysis and electromagnetic analysis of the RF module with Cadence electromagnetic solutions and Cadence thermal solutions.

The new 5G capabilities also require new high-performance, low-power digital blocks such as beamforming engines, channelizers, and signal conditioners. These highly algorithmic blocks are naturally modeled in C++ or SystemC®, which Cadence Stratus™ High-Level Synthesis (HLS) synthesizes to highly efficient low-power RTL for implementation with the Cadence Low-Power Solution. Moreover, with Stratus HLS, these same algorithmic blocks can be retargeted for other 5G applications with different requirements, ranging from ultra-Iow-power IoT sensors to high-performance basestations.

Tensilica IP

For digital baseband precoding/combining, beam measurement, and tracking in the 5G transceiver design, Cadence provides the Tensilica® ConnX B20 DSP IP, utilizing the latest Tensilica NX architecture for the 10Gbs and above data rates needed for 5G.

The Tensilica IP provides the needed throughput for 5G handset uplink and downlink, covering the functions of the New Radio-Physical Uplink Control Channel (NR-PUCCH), Uplink Shared Channel (NR-PUSCH), Random Access Channel (NR-PRACH), Downlink Control Channel (NR-PDCCH), and Broadcast Channel (NR-PBCH).

Verification of Chips, Packages and Board Designs

To verify the chip, package, or board designs, Cadence offers verification tools and hardware to speed these complex and very important tasks. The Cadence Palladium® Enterprise Emulation Platform is essential for emulating the design before the chip is finalized. Chip designs can be prototyped using the Cadence Protium™ S1 FPGA-Based Prototyping Platform, which enables early software validation and firmware development. The entire Cadence Verification Suite speeds chip verification, and our Sigrity™ signal integrity (SI) and power integrity (PI) integrated solutions enable fast validation of packages and board.

Tell Me More About 5G
  • Related Products

    • Virtuoso RF Solution
    • AWR Design Environment Platform
    • Prototyping
    • Electromagnetic Solvers
    • Thermal Solutions
    • Stratus High-Level Synthesis
    • SI/PI Analysis
    • Cadence Verification
    • Tensilica ConnX B20 DSP
News ReleasesVIEW ALL
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  • Cadence Expands Collaboration with Arm to Accelerate Mobile Device Silicon Success 06/28/2022

  • Cadence and Intel Foundry Services Collaborate to Accelerate Innovation with Scalable and Proven Cadence Cloud Solutions 06/28/2022

  • Cadence Achieves PCIe 5.0 Specification Compliance for PHY and Controller IP in TSMC Advanced Technologies 06/21/2022

  • Cadence Announces $100 Million Accelerated Share Repurchase Agreement 06/21/2022

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