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Digital Design and Signoff

Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.

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Custom IC / Analog / RF Design

Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.

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Verification

Offering a full verification flow to our customers and partners that delivers the highest verification throughput in the industry

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IP

An open IP platform for you to customize your app-driven SoC design.

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IC Package Design and Analysis

Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.

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Multiphysics System Analysis

Cadence® system analysis solutions provide highly accurate electromagnetic extraction and simulation analysis to ensure your system works under wide-ranging operating conditions.

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Embedded Software

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Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.

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US - English
  • China - 简体中文
  • Japan - 日本語
  • Korea - 한국어
  • Taiwan - 繁體中文
  • Products
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Integrity 3D-IC Platform
          • Cadence Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Voltus IC Power Integrity Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Spectre FX Simulator
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus-Fi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Virtual Prototyping
          • Emulation and Prototyping
          • Static and Formal Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
      • IP
        • PRODUCT CATEGORIES
          • 112G/56G SerDes
          • Chiplet and D2D
          • Denali Memory Interface and Storage IP
          • Interface IP
          • PCIe and CXL
          • Tensilica Processor IP
        • RESOURCES
          • Discover PCIe
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
      • Multiphysics System Analysis
        • PRODUCT CATEGORIES
          • Computational Fluid Dynamics
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Signal and Power Integrity
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Solver Cloud
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Fidelity CFD
          • Sigrity Advanced SI
          • Celsius Advanced PTI
          • RESOURCES
          • System Analysis Center
          • System Analysis Resources Hub
          • AWR Free Trial
      • Embedded Software
      • PCB Design and Analysis
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • Allegro X Design Platform
          • RESOURCES
          • What's New in Allegro
          • Advanced PCB Design & Analysis Resources Hub
          • Flows
      • Computational Fluid Dynamics
    • PERVASIVE INTELLIGENCE
      • AI / Machine Learning
      • AI IP Portfolio
    • CADENCE CLOUD
    • VIEW ALL PRODUCTS
  • Solutions
      • Industries
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • Hyperscale Computing
      • Technologies
        • 3D-IC Design
        • Advanced Node
        • AI / Machine Learning
        • Arm-Based Solutions
        • Cloud Solutions
        • Computational Fluid Dynamics
        • Functional Safety
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • Industries
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • Hyperscale Computing
      • Technologies
        • 3D-IC Design
        • Advanced Node
        • AI / Machine Learning
        • Arm-Based Solutions
        • Cloud Solutions
        • Computational Fluid Dynamics
        • Functional Safety
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • Industries
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • Hyperscale Computing
      • Technologies
        • 3D-IC Design
        • Advanced Node
        • AI / Machine Learning
        • Arm-Based Solutions
        • Cloud Solutions
        • Computational Fluid Dynamics
        • Functional Safety
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
  • Support
      • Support
        • Support Process
        • Online Support
        • Software Downloads
        • Computing Platform Support
        • Customer Support Contacts
        • Technical Forums
      • Training
        • Custom IC / Analog / RF Design
        • Languages and Methodologies
        • Digital Design and Signoff
        • IC Package
        • PCB Design
        • System Design and Verification
        • Tensilica Processor IP
      • Support
        • Support Process
        • Online Support
        • Software Downloads
        • Computing Platform Support
        • Customer Support Contacts
        • Technical Forums
      • Training
        • Custom IC / Analog / RF Design
        • Languages and Methodologies
        • Digital Design and Signoff
        • IC Package
        • PCB Design
        • System Design and Verification
        • Tensilica Processor IP
      • Support
        • Support Process
        • Online Support
        • Software Downloads
        • Computing Platform Support
        • Customer Support Contacts
        • Technical Forums
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        • Custom IC / Analog / RF Design
        • Languages and Methodologies
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5G Baseband and Edge Computing

  • 5G Systems and Subsystems
  • 5G Handset
  • 5G Radiohead
  • 5G Baseband and Edge Computing
  • 5G Fronthaul and Backhaul

In a centralized or cloud radio access network (C-RAN), baseband cabinets move from the bottom of mobile operator masts to edge-computing facilities in the fronthaul, where centralized baseband can be dynamically shared between radioheads. Massive co-located artificial intelligence (AI) is used to optimize the baseband performance over widely varying radiohead installations and traffic, and provide the AI heavy lifting for robots, drones, and other user equipment.

5G baseband and high-performance computing (HPC) meet in mobile edge-computing centers, and like HPC, the latest digital, network, and machine learning (ML) technologies are driving the market. Fundamental to this are digital design and signoff tools with class-leading power, performance, and area (PPA) outcomes on advanced nodes, where SoC designs incorporate increasing numbers of CPU and AI processor cores.

Tell Me More About 5G

 

To enable this, Cadence provides very high capacity Cadence® Advanced-Node Solutions for digital and analog, and Arm®-based solutions. But as these multicore HPC SoCs reach the limits of reticle size, there is also a move to disaggregated SoCs that combine heterogeneous chiplets on a substrate for yield and mixed-node benefits, and here Cadence provides 3D-IC Design Solutions with the UltraLink™ D2D PHY IP for chiplet interconnection. Finally, providing dense HPC in small mobile edge-compute centers demands very high-speed board designs via Allegro® PCB Designer High-Speed Option, and electromagnetic impact analysis of multi-fabric gigabit-speed signal pathways with Cadence Electromagnetic Solutions and system thermal analysis with Cadence Thermal Solutions.

Neural networks are now being developed and deployed in a wide range of markets, from communications to surveillance. The computational, power, and memory requirements to process this data are continuously increasing, with new networks and new ways to approach deep learning every day. The Cadence® Tensilica® DNA processor family offers a much-needed breakthrough in terms of energy efficiency and performance to meet the requirements of on-device artificial intelligence (AI), including AI software development and deployment. Cadence Cache Coherent Interconnect IP and DDR IP further complement the Cadence on-device AI. 

5G software stacks will be some of the largest and most complex in the industry. Early software development is critical for successful baseband and edge computing SoCs, and Cadence hardware verification platforms such as the Palladium® Z1 Enterprise Emulation System and the Protium S1 FPGA Prototyping Platform enable early software bring-up and development on work-in-progress SoC designs incorporating CPU and AI processor cores. TCAM is natively supported in the Palladium Z1 platform for SoC switch design.

For the highest-possible communication performance, Cadence provides the Cadence 112G SerDes IP. Its unique firmware-controlled adaptive power design provides optimal power and performance tradeoffs and more efficient system designs based on platform requirements. This DSP-based architecture provides superior data recovery for lossy and noisy channels.

5G infrastructure, in common with handset design, needs high-performance and highly algorithmic digital blocks for beamforming, channelizing, and signal conditioning. Modeled in C++ or SystemC®, these blocks are retargeted and synthesized by Stratus™ High-Level Synthesis (HLS) for the highly demanding requirements of high-performance baseband infrastructure and creating highly efficient, low-power RTL for implementation with the Cadence Low-Power Solution. 

Finally for the baseband itself, Cadence provides the Tensilica ConnX B20 DSP IP in multi-core configurations for precoding/combining, beam measurement, and tracking.

  • Related Products

    • Advanced-Node Solutions
    • Arm-Based Solutions
    • 3D-IC Design Solution
    • Allegro PCB Designer
    • Palladium Z1 Enterprise Emulation Platform
    • Protium S1 Desktop Prototyping Platform
    • Stratus High-Level Synthesis
    • Electromagnetic Solvers
    • Thermal Solutions
    • 112G SerDes IP
    • Tensilica DNA Processor
    • Ultralink D2D PHY IP
    • Tensilica ConnX B20 DSP
News ReleasesVIEW ALL
  • Cadence Digital Full Flow Achieves Certification for GlobalFoundries® 12LP/12LP+ Process Platforms 05/19/2022

  • Cadence’s John Wall and Richard Gu to Present at Needham Conference 05/06/2022

  • Cadence Reports First Quarter 2022 Financial Results 04/25/2022

  • Cadence Ushers in New Era of Performance and Accuracy for Multiphysics System Simulation with Fidelity CFD 04/19/2022

  • New Cadence High-Speed Ethernet Controller IP Family Enables Silicon-Proven Ethernet Subsystem Solutions up to 800Gbps 04/12/2022

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