To enable this, Cadence provides very high capacity Cadence® Advanced-Node Solutions for digital and analog, and Arm®-based solutions. But as these multicore HPC SoCs reach the limits of reticle size, there is also a move to disaggregated SoCs that combine heterogeneous chiplets on a substrate for yield and mixed-node benefits, and here Cadence provides 3D-IC Design Solutions with the UltraLink™ D2D PHY IP for chiplet interconnection. Finally, providing dense HPC in small mobile edge-compute centers demands very high-speed board designs via Allegro® PCB Designer High-Speed Option, and electromagnetic impact analysis of multi-fabric gigabit-speed signal pathways with Cadence Electromagnetic Solutions and system thermal analysis with Cadence Thermal Solutions.
Neural networks are now being developed and deployed in a wide range of markets, from communications to surveillance. The computational, power, and memory requirements to process this data are continuously increasing, with new networks and new ways to approach deep learning every day. The Cadence® Tensilica® DNA processor family offers a much-needed breakthrough in terms of energy efficiency and performance to meet the requirements of on-device artificial intelligence (AI), including AI software development and deployment. Cadence Cache Coherent Interconnect IP and DDR IP further complement the Cadence on-device AI.
5G software stacks will be some of the largest and most complex in the industry. Early software development is critical for successful baseband and edge computing SoCs, and Cadence hardware verification platforms such as the Palladium® Z1 Enterprise Emulation System and the Protium S1 FPGA Prototyping Platform enable early software bring-up and development on work-in-progress SoC designs incorporating CPU and AI processor cores. TCAM is natively supported in the Palladium Z1 platform for SoC switch design.
For the highest-possible communication performance, Cadence provides the Cadence 112G SerDes IP. Its unique firmware-controlled adaptive power design provides optimal power and performance tradeoffs and more efficient system designs based on platform requirements. This DSP-based architecture provides superior data recovery for lossy and noisy channels.
5G infrastructure, in common with handset design, needs high-performance and highly algorithmic digital blocks for beamforming, channelizing, and signal conditioning. Modeled in C++ or SystemC®, these blocks are retargeted and synthesized by Stratus™ High-Level Synthesis (HLS) for the highly demanding requirements of high-performance baseband infrastructure and creating highly efficient, low-power RTL for implementation with the Cadence Low-Power Solution.
Finally for the baseband itself, Cadence provides the Tensilica ConnX B20 DSP IP in multi-core configurations for precoding/combining, beam measurement, and tracking.