Cadence Cerebrus AI Studio

The Cadence Cerebrus^® AI Studio solution is the industry’s first agentic AI, multi-block, multi-user design platform for system-on-chip (SoC) optimization. It delivers high engineering productivity, reducing time to market by 5X to 10X. Cadence Cerebrus AI Studio enables the optimization of an entire SoC or a subsystem, consisting of many blocks with various design objectives within a single platform. With Cadence Cerebrus AI Studio, every engineer in the design team is empowered to implement multiple blocks concurrently, achieving massive parallelization. Multiple engineers using a common design platform, along with advanced techniques such as transfer learning across designs and smart model selection, brings a paradigm shift in design closure methodology. Data aggregated using advanced data analytics can quickly identify bottlenecks and converge critical designs, thereby reducing turnaround time.

We are amid an AI super cycle, and Cadence Cerebrus AI Studio is well aligned with Cadence’s Intelligent System Design Strategy. The traditional manual and iterative design flows make design implementation expensive, time-consuming, and highly reliant on an individual’s expertise. Cadence Cerebrus Intelligent Design Explorer (released in 2021) introduced automation for design optimization at the block level by using machine learning (ML) and distributed computing. Our vision at Cadence is to extend automation for SoC design closure. Cadence Cerebrus AI Studio brings together the power of agentic AI to enable new natural language-based user interactions and provides a platform for AI agents to coordinate tasks and workflows for both design creation and physical implementation. By utilizing AI agents that feature multi-step decision-making to achieve desired goals, Cadence Cerebrus AI Studio delivers engineering productivity and power, performance, and area (PPA) benefits via customized optimization methodologies for each block in the subsystem/SoC, delivering game-changing results.

The semiconductor industry is at an inflection point within its history. The latest technological advancements in AI, quantum computing, 5G, virtual and augmented reality, IoT, autonomous driving, and biotechnology have revolutionized the semiconductor industry. The growing demands of AI workloads and sophisticated model training are spurring highly specialized semiconductor chips with intricate functionalities and high-performance compute. The transistor count continues to scale with integration and cutting-edge multi-die architectures. Instead of one core, there are eight cores. Instead of having just CPUs, there are neural engines, GPUs, and more. Using the most advanced process nodes, achieving lowest power, highest performance, and smallest possible die size, along with the shortest time to market are some of the most important factors for semiconductor companies to consider in this fast-paced, consumer-driven environment.

Naturally, the question arises as to how do we sustain this massive outburst of demand for complex semiconductor content. The industry is grappling with accelerated design cycles and a shortage of design experts. Although change is hardly new within the semiconductor landscape, the recent burgeoning technologies require a more automated approach. EDA has been at the forefront in making chip design easier and enhancing productivity. The next major frontier is agentic AI automation, which aims to meet this aggressive growth by elevating performance and productivity to new heights. As a leader in applying AI to design implementation, Cadence’s vision is to use the most advanced AI technology to optimize an entire SoC within a single platform with a small design team. This approach brings a generational shift from a fleet of designers optimizing a single block to a single engineer designing multiple blocks. Discover how Cadence Cerebrus AI Studio leverages the most advanced agentic AI technology, deploys intelligent workflows orchestrating entire SoC/subsystem optimization and closure, and transforming semiconductor design implementation methodology.

Cadence Cerebrus AI Studio offers a very powerful design dashboard that can be used to create projects, start Cadence Cerebrus runs, and analyze the data generated across all the designs. Using the dashboard, the entire team can work within the same framework and do full-flow design optimization to bring their respective blocks to closure without leaving the infrastructure.

Dashboard View

The dashboard view provides a complete chip-level status of the project. This feature is extremely useful for knowing the progress of each block within the project and identifying bottlenecks. It provides a holistic picture of a project.

Analysis View

The analysis view does a comparison across different projects. Graphs, charts, metrics, and comparative data can be generated and analyzed using advanced data analysis for faster design debug and closure.

The design dashboard is a collaborative space for designers working on different blocks of a project. This feature allows design team members to view each other's runs and scenarios, compare data, learn, and apply this information to their design for better and smarter design closure.

Cadence Cerebrus AI Studio is a multi-user, multi-block, agentic AI design platform. It can support any number of designs within a project or across projects. It supports a framework where a project is created, and within a project, multiple blocks can be optimized simultaneously by one or more engineers, bringing massive parallelization.

Cadence Cerebrus Exploration and Optimization Agents

During a design life cycle, multiple runs are performed before the design is finally ready for tapeout. Any given design will have multiple versions of RTLs or netlist drops with some functionality change before the design is frozen. Sometimes, constraints are updated that trigger a new version of a design. An input collateral, such as a standard cell library version, may also trigger a new design version. All these design versions call for many design runs, which are seamlessly managed by Cadence Cerebrus AI Studio using Cadence Cerebrus Intelligent System Explorer to find the best solution. It deploys various AI agents, such as PPA Optimization, Floorplan Optimization, Clock Tree Optimization, and many more, to optimize the design and bring it to closure.

Smart Model Selection

Cadence Cerebrus AI Studio provides a very efficient mechanism to transfer learnings from pre-trained models to new runs spanning different versions of the same design or spanning different designs and projects, accelerating design closure time while also enabling efficient compute resource usage. Every time a run is made, AI agents are available to automatically train models at various levels of the design hierarchy—whether at the design level or the project level. As new Cadence Cerebrus runs are made, AI agents incrementally train these models. Over time, a library of ML models will be created. With the smart model selection feature of Cadence Cerebrus AI Studio, the AI agents auto-suggest a model based on the design requirement. These models can be replayed to serve as a seed for a new run to start further exploration or can be reused to close the design without further exploration.

Owing to technological advancements, today’s semiconductor chips must be highly sophisticated to support multiple functionalities on a SoC and usually consist of many trillions of transistors. As a result, designing these chips flat is not feasible, as the run time will skyrocket and the design methodology will be inefficient. SoCs must be partitioned into multiple blocks, and each block is then designed individually. This process is very iterative and, as of today, requires a fleet of engineers to bring the SoC to closure.

The top and block should be co-optimized. While there is top-down feedback for the block area, shape, budgets, pin placement, and more, there is also block-to-top feedback for many critical blocks. At the same time, when a new RTL drop comes in, the entire process from partitioning, floorplanning, block implementation, and assembly must be redone. This requires careful data handoffs and can be error-prone and very time-consuming. The entire process calls for immense collaboration and efficiency between various teams implementing different hierarchies to bring closure at the block and top level.

Cadence Cerebrus AI Studio can perform hierarchical design closure more efficiently by employing agentic AI features that autonomously handle top-block co-optimization, providing game-changing engineering productivity and turnaround time.

This allows the simultaneous exploration of top and blocks with various actions and policies. Multiple data handoffs are handled with tagging, and all the design changes can be embraced with live updates. AI agents assist the design closure at every stage of hierarchical design, and the Cadence Certus Closure Solution can be used for chip-level timing closure.

Cadence Cerebrus AI Studio can be used for hierarchical design at every stage of the design flow. For the prototype stage, this feature provides a usable top floorplan with reasonable channel estimation and module placements, which can be used for I/O bump/pad planning, packaging simulations, PG bump distribution and supply planning, and PCB planning. Once more mature RTLs are delivered after design flow flush, explorations begin, and winning recipes from the Partition Optimization agent will be taken forward for clock planning and budgeting, and then handed off for block exploration.

Top exploration can also start in parallel with early-ILMs. When prects block results are available after going through Cadence Cerebrus-based optimization, the top can migrate to using prects databases for exploration. The purpose of this exploration is to arrive at predictable PPA convergence for blocks and top, and to determine what should be frozen for subsequent iterations and what can be kept open for further exploration.

Also note that, for convergence-critical blocks that are unable to close in congestion or timing, use bottom-up partitioning with the critical block shape frozen, so that other blocks can adjust to accommodate it. Once the design reaches the pre-final stage, ML model reuse should be applied to transfer the learnings of previous partition optimization exploration regarding block shapes, location, pin placement, etc., to the incoming mature Innovus database. All subsequent stages will run in an “Incremental” mode, and all block/top stage apps will run in “Warm-start’ mode.

The final design netlist goes through a high degree of reuse of all past experiments, frozen partitions, top clock planning, and budgeting, only accommodating minor changes that are incrementally handled. All stage-wise apps run in “Replay” mode, where the smart/mega replay techniques can be used as appropriate.

Partition Optimization

The Partition Agent takes the Innovus platform’s top-level database with logical partitions and outputs block level databases that are optimized for the top level, using Cadence Cerebrus infrastructure. These blocks can be individually designed within the Cadence Cerebrus AI Studio platform.

Integration Optimization

The Integration Agent is used to assemble the optimized blocks of a subsystem to create the top. It explores the best combination of block scenarios that yield the best quality of results at the top. IntegrationOpt evaluates the block level scenarios to create an optimized top level. The user can control the exploration by providing different objectives, such as timing and power.