White Papers

Streamlining Functional Verification for Multi-Die and Chiplet Designs

Cache-Coherent Symmetric Multiprocessing with LX8 Controllers on HiFi DSPs

Accelerating High-Lift Aerodynamics: Automated Meshing for CFD Excellence

Designing for Reliability with a System Life Estimator

Designing Data Centers for Increasing IT Densities and AI Workloads

A New RF Platform for Silicon MMIC and System Design

Cadence Cerebrus AI Studio

Agentic AI, Multi-Block Multi-User SoC Design Platform

Cadence Innovus+ Synthesis and Implementation System White Paper

Integrated RTL to GDS Chip Design Delivering Accelerated Results

Allegro X AI for Generative System Design

The cloud-based Cadence Allegro X AI system design technology leverages generative AI and search to synthesize PCBs directly using physics-based analysis and high-level design goals.

Autodesk and Cadence: Seamless ECAD and MCAD Collaboration

Thermal Analysis of 3D Stacking and BEOL Technologies with Functional Partitioning of Many-Core RISC-V SoC

Application of External CFD Modeling in Data Center Design

Fully Coupled CFD Simulations for Micro Gas Turbine Engines

High-Fidelity Noise Prediction for Aerospace and Automotive Industries

Power Module Design for Electric Vehicles – Addressing Reliability and Safety

Radar-based Vital Signs Detection for In-cabin Applications

Data Center Digital Twin Return on Investment from an Environmental Standpoint

Cabin Comfort: Aeroacoustics Simulation for Car Interior Noise Prediction

GPU-Accelerated Large-Eddy Simulations of NASA Fan Noise

Intel and Cadence Collaboration on UCIe: Demonstration of Simulation Interoperability

A UCIe Case Study

Bird’s Eye View on Tensilica Vision DSPs

August 2024

Aeroacoustics Large-Eddy Simulation of VTOL Aircraft Design

Cadence Janus NoC

How Does Reclaiming Data Center Lost Capacity Result in Return on Investment?

Effectiveness of long-term data center management solutions, maximizing efficiency via capacity recovery

Steady and Unsteady Full-Engine Simulations

New Meshing Methods for Ship Propellers and Hydrofoils

Advancing the Future of Hearing Aids with Cadence

Cadence Cerebrus in SaaS and Imagination Technologies Case Study

Sigrity X - Redefining Signal and Power Integrity

3D Connection Artifacts in PDN Measurements

Demystifying Mixed-Signal Simulation for Digital Verification Engineers

Bridging the Gap Between Industry and Academia

Intelligent System Design

Computational Software

3D-IC Design Challenges and Requirements

SLAM and DSP Implementation

20nm Design

How this Advanced Technology Node Will Transform SoCs and EDA

Cloud—The Future of Electronic Design Automation

How the Productivity Advantages of High-Level Synthesis Can Improve IP Design, Verification, and Reuse

800G Ethernet MACsec Integration and Verification

Thermal Warpage Simulation of a Temperature-Dependent Linear Elastic Material Package

Thermal and Stress Analysis of 3D-ICs with Celsius Thermal Solver

Designing High-Performance Electronics for Today’s Hyperconnected Systems

How a Team-Based Approach to PCB Power Integrity Analysis Yields Better Results

Three Ways that Allegro TimingVision Environment Speeds Up Timing Closure of High-Speed PCB Interfaces

Automating Inter-Layer In-Design Checks in Rigid-Flex PCBs

Building Differentiated Products Through Shorter, More Predictable Design Cycles

TIE Language—The Fast Path to High-Performance Embedded SoC Processing

Meeting Multiple IoT Application Requirements with a Single, Configurable DSP Core

Fixed-Point and Floating-Point FMCW Radar Signal Processing with Tensilica DSPs

Tensilica DSPs Support in Eigen Library

Tensilica DSP Code Generation Toolbox with MATLAB/Simulink

Moving to the Next Level of Autonomous Driving Through Advanced, Extensible DSPs

HiFi 1, an Ultra-Low Energy DSP for TWS, Bluetooth Headset, and Always-on Applications

IP Solutions for a Data-Centric World

Accelerate Adoption of High-Speed, Low-Latency, Cache-Coherent Standards Using Formal Verification

Interop Shift Left: Using Pre-Silicon Simulation for Emerging Standards

A CXL Case Study

Efficient Verification of Mixed-Signal SerDes IP Using UVM

Leveraging Multi-Protocol PHY for PCIe to Cope with SoC Design Complexity

Addressing the “Power-Aware” Challenges of Memory Interface Designs

Overcoming Signal, Power, and Thermal Challenges Implementing GDDR6 Interfaces

Power-Aware Analysis Solution

Backchannel Modeling and Simulation Using Recent Enhancements to the IBIS Standard

How to Achieve 10X Faster Power Integrity Analysis and Signoff

Unified Compression and LBIST in a Physically Aware Environment

Automated HW/SW Co-Design of DSP Systems Composed of Processors and Hardware Accelerators

Techniques to Accelerate Power and Timing Signoff of Advanced-Node SoCs

Compressing Datasets Created During Silicon Design

Hierarchical Timing Analysis: Pros, Cons, and a New Approach

Accelerate Algorithm to Silicon Development with Stratus HLS

How High-Level Synthesis Was Used to Develop an Image-Processing IP Design from C++ Source Code

Methodology helped accommodate late spec changes on aggressive delivery schedule

Case Study: Blu Wireless Boosts SystemC Design and Verification Productivity Using High-Level Synthesis Technology

Best Full-Flow PPA

Using High-Level Synthesis to Design and Verify 802.11ah Baseband IP

A Faster, More Accurate Approach for System-Level Performance Verification of a Wireless RFIC Design

Consolidating RF Flow for High-Frequency Product Design

Plan-Based Analog Verification Methodology

Revolution by Evolution: Getting to the Next Technology Breakthrough in Analog Simulation

Analog Reliability Analysis for Mission-Critical Applications

Accelerating Monte Carlo Analysis at Advanced Nodes

Addressing Memory Characterization Capacity and Throughput Requirements with Dynamic Partitioning

Addressing Process Variation and Reducing Timing Pessimism at 16nm and Below

Liberate Characterization Portfolio

A complete solution for fast and accurate characterization and validation

PVS Interactive Short Locator: Establishing Efficiency and Predictability in the LVS Short Debug Process for Advanced SoC Design

Radar-based Multi-target Tracking on ConnX 110 DSP

March 2023

Is it Necessary to Make Great DSPs Greater?

Why a DSP is Indispensable in the New World of AI

Chiplets and Heterogeneous Packaging Are Changing System Design and Analysis

Unleashing the Power of Generative AI in Chip, System, and Product Design

Overcoming Signal Integrity Challenges of 112G Connections

Accelerating Monte Carlo Simulations for Faster Statistical Variation Analysis, Debugging, and Signoff of Circuit Functionality

Machine Learning-Driven Full-Flow Chip Design Automation

Impact of Finite Interconnect Impedance Including Spatial and Domain Comparison of PDN Characterization

How to Speed Up Large-Scale EM Simulation of ICs Without Compromising Accuracy

FMEDA-Driven SoC Design of Safety-Critical Semiconductors

Accelerating Monte Carlo Analysis at Advanced Nodes