Technical Brief
System VIP
Overview
Overview
As system-on-chip (SoC) design complexity continues to increase, the verification of a fully assembled chip with all its IP components, buses, and interfaces has become the critical path to tapeout. Chip-level testbench creation, bus traffic generation, bus performance bottleneck identification, and data and cache coherency verification all lack automation. The effort required to complete these tasks is error-prone and time-consuming. Missed performance bottlenecks can expose architectural-level oversights late in the project, and covering all corner cases for cache coherency across multiple parallel compute engines can take months.
Cadence System-Level Verification IP (System VIP) takes Cadence’s market leadership in IP-level verification automation and brings it to the chip level. It consists of a suite of tools and libraries, each working seamlessly with Cadence’s simulation, emulation, and prototyping engines.
Cadence System VIP includes:
-
System Testbench Generator allows users to describe their testbench topology through IP-XACT or CSV and automatically generate a ready-to-use UVM SystemVerilog testbench for simulation or C testbench for emulation. - System Traffic Library provides users with rich portable stimulus tests for common SoC domains, including coherency, performance, PCI Express® (PCIe®), and NVMe subsystems, which run seamlessly in simulation, emulation, and final silicon. These libraries are integrated with Cadence VIP and Accelerated VIP (AVIP) for fast bring-up.
- System Performance Analyzer offers comprehensive performance analysis for memory subsystems, bus interconnects, and peripherals.
- System Verification Scoreboard provides data and cache-coherency checkers, allowing users to check data consistency across the system to support both simulation and emulation flows. The automated scoreboard supports coherent interconnects, memories, and peripherals and is integrated with Cadence VIP and AVIP.
System Testbench Generator
The System Testbench Generator allows users to describe their testbench topology through IP-Xact or CSV and automatically generate a ready-to-use UVM SystemVerilog testbench for simulation or C testbench for emulation.
- For exhaustive functional verification, the System Testbench Generator generates fully functioning UVM SystemVerilog environments, complete with VIP, scoreboard, clock and reset generation logic, test sequences, routing model with system memory map, and more.
- For subsystem and system integration verification, the System Testbench Generator generates C-based verification environments that can run in simulation or in Cadence Palladium and Protium hardware platforms.
Use Flow
The System Testbench Generator builds the verification environments by instantiating and configuring the Verification IP and the System Verification Scoreboard. It enables test generation from System Traffic Libraries, which are portable from the IP to the subsystem to the SoC levels.
Main Capabilities
- Generation of fully functioning UVM SystemVerilog verification environments from user-supplied meta-data for simulation flow
- Generation of C-based verification environments from user-supplied meta-data for simulation, acceleration, and emulation flows
- Support of functional verification and performance analysis
- Fully compatible with Cadence Perspec System Verifier for the creation of portable stimulus
- Per user configuration, generated environments include Simulation VIP (VIP), Acceleration VIP (AVIP), system-level scoreboard, routing model with system memory map information, pre-generated ready-to-use tests, and more
System Traffic Library
The System Traffic Libraries provide out-of-the-box scenarios to verify common SoC integration verification domains. The integration challenges involve mixing scenarios that cross multiple functional features (power, coherency, DVM, I/O, PCIe, etc.) that are hard to achieve using manual schemes. The System Traffic Library scenarios are written in PSS (Portable Test and Stimulus Standard), so they are applicable for both pre-silicon verification and post-silicon validation and can be implemented on simulation, emulation, rapid prototyping (FPGA), and silicon platforms. They are also integrated with Cadence VIP to implement these scenarios on pre-silicon simulation and emulation platforms.
The System Traffic Libraries are supported for multiple architectures, including Arm® v8/v9 and RISC-V.
The following System Traffic Libraries are available:
- Coherency Library
- PCIe Integration Library
- Performance Library
Usage Flow
The System Traffic Libraries come with a user-editable configuration sheet to capture critical system information that is used to configure the library scenarios. The scenarios can be extended further or mixed with user code to create custom scenarios.
The System Traffic Libraries can be generated as C/C++ code and run through the CPU in the design for "embedded flow" or in a "coreless" flow. In these flows, the protocol-related traffic goes through VIP or AVIP in simulation or emulation.
Coherency System Traffic Library
To address system coherency testing, the main features of the Coherency System Traffic Library include:
- Out-of-the-box verification plan and test suite for heterogeneous multi-core cache-coherent processors
- Ability to visualize scenarios and analyze coverage before test implementation
- Support for Arm v8/v9 and RISC-V architectures
PCIe Integration System Traffic Library
To address PCIe SoC integration challenges, the main features of the PCIe Integration System Traffic Library include:
- Out-of-the-box verification plan and test suite for I/O-coherent PCIe root port and end point
- Ability to visualize scenarios and analyze coverage before test implementation
- Includes tests for memory, ATS, deadlocks, power down, register access, and more
Performance System Traffic Library
To analyze system performance using traffic profiles and benchmark scenarios, the main features of the Performance System Traffic Library include:
- Out-of-the-box test suite for industry benchmarks and synthetic traffic profile tests
- Ability to visualize scenarios and analyze coverage before test implementation
- Post-processing to analyze performance results
- Work in conjunction with the System Traffic Generator
Test plans are provided for:
- Lmbench (Memory Read/Write/Copy)
- Dhrystone (Simple integer arithmetic, character/single/array operation, pointer/memory access)
- Coremark (matrix manipulation statemachine, cRC)
- Gzip (compress/uncomplex algorithms)
- Synthetic adaptive traffic profiles (ATP) for min latency and max bandwidth scenarios
System Performance Analyzer
The System Performance Analyzer is focused on identifying the performance degradation caused within memory subsystems, interconnects, and peripherals of a typical SoC, which must manage the conflicting performance goals of the various initiators within the system.
The performance goals within the system can be:
- Latency critical, which indicates the SoC must meet the maximum acceptable latency requirements
- Bandwidth critical, which indicates the SoC must meet the minimum acceptable bandwidth requirements
- Real time, which indicates the SoC must meet the maximum acceptable latency and the minimum acceptable bandwidth requirements
The following figure shows the system performance demands on the memory subsystem.
Use Flow
The System Performance Analyzer offers a comprehensive performance analysis for memory subsystems, interconnects, and peripherals with a single view for both simulation and emulation.
The System Performance Analyzer collects and records the transaction information in the System Performance Analyzer database. The System Performance Analyzer server then processes the transactions and presents the Performance Analysis views of the data to determine if the performance behavior of their design meets the criteria of their target application. The performance views are similar for both simulation and emulation environments.
Main Capabilities
- Enables discovery and debugging of performance degradation within memory subsystems
- Unified analysis across simulation and emulation platforms
- Latest web technology intuitively presents analysis results
- Uses strong, industry-standard database technology for capacity and scalability
- Complements existing VIP/MM and AVIP/MMP technologies on Cadence Xcelium and Palladium platforms for easy deployment
- Includes analysis diagrams for bus utilization, dynamic frequency, and DDR addressing
- Detailed analysis for page Hit/Miss and page utilization
- Visualizes the AMBA-DRAM transaction correlation for easy debugging
System Verification Scoreboard
With the rapid evolution of chip design and verification, the SoC contains multiple processors with caches and cache-coherent agents beyond the multi-processor clusters. Cache coherency, long regarded as one of the most complex verification challenges due to the address changes and data transformations happening in the SoC, requires an advanced and highly automated approach at the SoC level.
The System Verification Scoreboard enables the user to verify the data integrity of the system flows at the different levels of the SoC. The System Verification Scoreboard works with VIP to verify that each data flow strictly adheres to the given communication protocol. The System Verification Scoreboard checks for the proper functionality of coherent systems, flagging out all coherency violations. The System Verification Scoreboard is a flexible system-level scoreboard that can be extended to verify any design-specific functionality. The System Verification Scoreboard supports both real-time simulations and post-processing modes used in simulation and emulation environments, thus making it an ideal scoreboarding tool in any functional verification or performance validation tasks.
Use Flow
The System Verification Scoreboard provides data and cache coherency checkers, allowing users to check data consistency across the system and supporting both simulation and emulation flows. The automated scoreboard supports coherent interconnects, memories, and peripherals and is integrated with Cadence VIP and AVIP. The System Verification Scoreboard can be used for the full SoC, interconnect, or subsystems in both simulation and emulation platforms.
Main Capabilities
The main System Verification Scoreboard features and capabilities include:
- Out-of-the-box support of coherent, non-coherent, and cascading interconnects
- Provides API allowing connection of customer-proprietary VIP and/or bus monitors
- Seamlessly runs on Cadence Palladium Z1, Xcelium, and third-party simulators
- Supports any number of ingress, egress, and intermediate interfaces
- Supports all data transformations within and across protocol boundaries including splitting, upsizing, and downsizing
- Supports system-level "L3" cache (SLC)
- Supports Distributed Virtual Memory (DVM) transactions
- Enables user's extension for any design-specific checks
Summary
Using System VIP, Cadence customers creating SoCs in hyperscale, automotive, mobile, and consumer applications can automate chip-level verification and improve efficiency tenfold over existing homegrown methodologies.