RF/Microwave Design Software

To meet the demand for increased data rates and capacity, communications, aerospace/defense, and automotive applications are utilizing more bandwidth, millimeter-wave (mmWave) spectrum, and spatial efficiency vis-a-vis multiple-in-multiple-out (MIMO) and beam steering phased arrays. Along with a need for small form-factor, cost-sensitive devices, RF to mmWave front-end components continue to evolve in order to keep pace with these new system requirements, the demands of enabling technologies, and space/cost considerations.

Engineering teams addressing these performance, integration, and cost/space goals face time-to-market pressures while striving to meet these increasingly complex product requirements. Engineers trying to bring these products to market need best-in-class simulation technology and design automation to accurately predict the performance of larger, densely integrated circuits/ subsystems designed for broadband and mmWave

spectrum. In addition, since these products are developed by diverse engineering teams across multiple design tools, RF design software must provide interoperability with the broader class of EDA used in the development of mixed-signal electronic systems. To optimize product development throughput and successful designs, this software must offer automation that supports engineering productivity alongside seamlessly integrated circuit, system, and electromagnetic (EM) simulation, synthesis, and optimization. These capabilities are built into Cadence AWR Design Environment software, inclusive of AWR Microwave Office, AWR Visual System Simulator(VSS), AWR AXIEM, and AWR Analyst software, providing a robust and complete platform for RF/microwave engineers to develop next-generation communication and radar front-end electronics. 

Furthermore, with the Version 15 (V15) release of its AWR Design Environment software, Cadence is addressing RF/ microwave design and integration through the company’s Intelligent System Design strategy, which delivers computational software capabilities across all design elements of electronic systems. At the core of this strategy is design excellence, including an optimized EDA portfolio of tools with best-in-class RF, microwave, and mmWave circuit, system, and EM analysis, IP for semiconductor, package, and PCB design, and scalable access in the cloud.

AWR Design Environment V15 offers key new and improved technologies that provide greater design efficiency and first-pass success to engineering teams developing and integrating III-V and silicon (Si) integrated circuits (ICs), multi-technology modules, and PCB assemblies. Engineering productivity is improved with new analyses, faster and higher capacity simulation technologies, time-saving design automation, and 5G New Radio (NR)-compliant testbenches that support power amplifier (PA) and antenna/array design, EM modeling, and RF/ microwave integration across heterogenous technologies.

New design environment and automation features help individual engineers and engineering teams be more efficient in their design entry, data display, and project management. Designers can adjust optimization goals directly from response plots, route design rule-compliant intelligent nets (iNets) in real-time, import Gerber-based layout designs into AWR Design Environment for EM analysis, and provide more user capabilities for the design task at hand. 

Addressing the increasing size and complexity of RF/ mixed-signal electronic systems, the new, faster layout and 3D viewer rendering capability in V15 enables users to zoom in and out and rotate large structures to inspect the physical design from any and all angles without any lag time. Large boards imported as IPC-2581 or ODB++ files from Cadence Allegro® PCB Designer or other layout tools can be readily inspected visually before editing and preparation for EM analysis using the PCB editing wizard.

In addition, V15 of AWR software expands support for RF/ microwave front-end component integration within multi-technology systems. The layer process definition file (LPF) in AWR Microwave Office defines the processing layers and parameters for the physical layout design. For analysis of heterogeneous substrates and multi-chip modules utilizing different semiconductor processes and laminates, AWR Design Environment software supports multiple process definitions within a single hierarchical project. The software’s “per-process technology” native LPF units, allow different processes to specify units that are most appropriate for a given technology (e.g., mils or microns). 

To meet bandwidth requirements, 5G systems aggregate contiguous and discontiguous spectrum at sub-6GHz and take advantage of the available bandwidth at mmWave frequencies, both of which put pressure on PA designers who need to address linearity and efficiency concerns in the presence of high peak-to-average power ratios (PAPRs).

In wideband PAs, baseband impedance variations over bandwidth can impact device linearity, resulting in intermodulation distortion (IMD) levels that vary asymmetrically with instantaneous signal bandwidth. This issue, which is associated with memory effects, is commonly addressed by using video bypass capacitors to terminate the baseband impedance with short circuits.

However, performance can be improved by considering alternative baseband impedance conditions. For instance, PA developers have shown significant improvements in linearity when active, baseband injection architectures such as envelope tracking (ET) are employed.

V15 of AWR software allows designers to optimize PA linearity performance through video band load-pull analysis of PAs operating under two-tone excitations. Designers can plot IMD and third-order intercept point (IP3) results as a function of (F2-F1) impedance, directly investigating intermodulation products over swept input power.

Load-pull analysis also supports impedance tuning at the 4th and 5th harmonics as well as the ability to generate contours on rectangular plots for enhanced visualization of performance versus load impedance.

Transistors designed for mmWave amplifier designs have high gain at lower frequencies, making them more prone to potential spurious oscillations. Stability analysis is critical to amplifier design and optimization, especially for these high-gain devices.

The commonly used K- and μ-factors, derived from linear circuit simulation, can accurately predict whether a 2-port network is unconditionally stable, yet they cannot detect instabilities for multi-stage amplifiers or devices connected in parallel. Other stability analyses such as NDF and loop gain techniques, can overcome these limitations but do so at the cost of extensive computations, making them too slow for performing optimization.

The loop gain envelope technique for evaluating the envelope of traditional loop gain stability circles has been shown to cut the simulation time of this more rigorous approach to stability analysis from hours down to seconds, making it ideal for stability optimization. V15 of AWR software supports this method with a loop gain envelope code module and equation block that can be easily applied to new amplifier designs. The support for loop gain envelope stability analysis offers designers the following benefits:

The loop gain envelope technique for evaluating the envelope of traditional loop gain stability circles has been shown to cut the simulation time of this more rigorous approach to stability analysis from hours down to seconds, making it ideal for stability optimization. V15 of AWR software supports this method with a loop gain envelope code module and equation block that can be easily applied to new amplifier designs. The support for loop gain envelope stability analysis offers designers the following benefits:

The characteristic impedance and electrical length (delay) of transmission lines represent two important design parameters used to control the frequency-dependent circuit response of passive RF/microwave circuits such as quarter-wave impedance transformers, Wilkinson power dividers/combiners, hybrid couplers, filters, and more.

Using AWR Design Environment V15, designers can directly synthesize the physical attributes (width, length) of these microstrip, stripline, or coplanar waveguide structures for a given substrate based on the desired electrical characteristics.

Likewise, the electrical characteristics can be calculated directly from the physical properties of the single or edge-coupled transmission line placed in the schematic. Synthesis of circuit model parameters provides vital data for generating accurate layout of these transmission lines without having to invoke the transmission line calculator and manually transfer the results into the transmission line property dialog box.

To enhance the speed and capacity of EM analysis for IC, package and board structures, AWR AXIEM meshing and solver technologies have undergone several key improvements, resulting in improved mesh quality for faster simulation run times and the ability to solve larger problems with a reduced mesh.

AWR Design Environment V15 can now detect and remove problematic mesh facets automatically with robust healing of high aspect ratio facets (HARF). The software supports subnanometer (nm) z-axis resolution of metals and dielectrics (previously rounded to the nearest nm), to provide faster modeling of sub-nm multi-layer IC structures such as metal-insulator-metal (MIM) capacitors.