Akeana Case Study

Akeana specializes in high-performance RISC-V processor IP, interconnect IP, and system IP, providing scalable and configurable solutions for next-generation AI chips and other compute-intensive workloads. The company enables SoC developers to leverage RISC-V-based solutions across a broad range of applications, including AI, cloud infrastructure, networking, data centers, mobile computing, and automotive.

With expertise in multicore architectures, accelerators, data movement engines, and compute subsystem interconnects, Akeana delivers customizable IP targeted at the RISC-V ecosystem. These IP are designed to optimize performance, power efficiency, and scalability. The company helps customers develop efficient, high-performance SoCs tailored to their needs by offering flexible compute subsystem solutions supporting coherent and non-coherent architectures.

Akeana faced several challenges entering the RISC-V IP space. As a startup with a bold vision, the company needed to develop tools and methodologies from the ground up to support advanced computing demands. Operating in a rapidly evolving industry, the engineers relied on their in-depth expertise to establish a strong foundation while remaining adaptable to technological changes. As Nitin Rajmohan, Co-founder at Akeana, explained, “As a startup, we leveraged our decades of experience in silicon innovation to overcome challenges and achieve next-generation computing with minimal resources.”

Optimizing development cycles while working within a startup-sized engineering team required Akeana to be highly efficient in its operations. The company prioritized rapid design cycles and pre-silicon validation, enabling customers to begin software development significantly earlier, thus accelerating product readiness. Their ability to maximize output with minimal overhead led to innovative solutions.

Akeana’s highly talented and motivated engineers embraced an iterative development cycle that required rapid advancements in verification. Functional verification became a critical focus as the interaction of advanced design elements increased complexity exponentially. Rajmohan noted, “Achieving high performance is not about a single magic feature. It takes an iterative process where you build, test, refine, and repeat. The faster we move through this cycle, the better our results.” To succeed, Akeana needed tools and workflows that provided efficiency while keeping pace with tight development schedules.

To address verification challenges and meet rigorous design demands, Akeana adopted Cadence’s Xcelium Logic Simulator, Palladium Emulation Cloud, and Verisium Debug as part of an integrated simulation, emulation, and debugging approach. These tools provided accelerated verification, improved design accuracy, and early software validation, ensuring the company’s vast IP portfolio was market-ready.

Akeana relied on Xcelium for early-stage verification, ensuring functional correctness before advancing to emulation. The simulator’s optimized computational kernel enabled high-speed execution, allowing engineers to test new features and validate design behavior efficiently. The tool was easily integrated with the model, allowing engineers to set up the environment quickly, reducing bottlenecks in the verification process, and ensuring rapid feedback on design changes.

By integrating Xcelium, the team reduced the time spent on simulation setup and improved efficiency in managing the rapid refinement required for their designs. This implementation allowed engineers to detect issues early in the design cycle, minimizing disruptions before progressing to full-system validation.

For comprehensive system-level validation, Akeana integrated Palladium, allowing engineers to evaluate hardware and software interactions before silicon availability. Full-system emulation allowed real-world software execution with fidelity debug capability, giving the design team deep insights into system performance and functionality under realistic workloads.

This early validation approach proved critical in detecting and resolving performance constraints before tape-out. By running actual software on the hardware design, Akeana could identify architectural inefficiencies and optimize performance long before fabrication. As Rajmohan described, “We start by making a feature change, run simulations to verify it is working, move to emulation, debug any issues, and repeat the process, completing the entire cycle in just two days.” Palladium enabled faster design iterations, significantly reducing the risk of late-stage failures.

The company implemented Verisium Debug, Cadence’s advanced AI-integrated platform, to accelerate troubleshooting and enhance issue resolution. The tool gives engineers visibility into all verification stages, enabling them to quickly isolate, analyze, and resolve functional issues, reducing manual debugging efforts.

Additionally, with seamless integration across Cadence’s verification flow, Verisium Manager provided comprehensive traceability from simulation to emulation, enabling engineers to track the impact of design changes and optimize verification coverage. This tool is key in eliminating known inefficiencies and ensuring that Akeana’s high-performance IP meets stringent reliability standards before final implementation.

With Cadence’s verification solutions, Akeana streamlined development within a small resource profile and successfully delivered high-performance RISC-V IP. The combination of Cadence verification tools allowed the team to iterate through design cycles multiple times a week, significantly improving productivity within a lean engineering environment. As Nitin Rajmohan explained, “As a startup, our assembled team utilized its decades of prior experience in silicon innovation to address challenges and achieve next generation computing with limited resources.”

Cadence’s tools helped simplify the company’s verification process, allowing them to focus engineering efforts on performance improvements rather than manual debugging overhead. Pre-silicon validation enabled Akeana’s customers to begin software development earlier, ensuring that potential issues could be addressed before fabrication and reducing the likelihood of late-stage design failures. As Rajmohan noted, “Qualifying our IP in real-world software even before silicon increases the confidence in the quality of our IP.”

By leveraging Cadence’s integrated verification solutions, Akeana reduced performance barriers, optimized design refinements, and accelerated debugging. Verisium allowed engineers to quickly pinpoint functional issues, reducing the time spent on manual troubleshooting. The seamless combination of these verification tools allowed the company to meet aggressive performance goals while maximizing limited engineering resources.

Business Challenge

  • Developing tools and methodologies from the foundation up
  • Maximizing development efficiency with minimal resources
  • Accelerating pre-silicon validation

Design Challenges

  • Managing functional verification complexity
  • Ensuring full system emulation
  • Improving debugging efficiency

Cadence Solution

  • Xcelium Logic Simulator
  • Palladium Emulation Cloud
  • Verisium Debug
  • Verisium Manager
  • Accelerated iteration cycles, enabling design refinements multiple times per week
  • Enabled pre-silicon validation, allowing customers to begin software development earlier and reducing late-stage risks
  • Improved debugging efficiency through automated issue correlation and faster resolution of verification bottlenecks