Brochure

Denali Controller IP for DDR

LPDDR5/4X/4/3 and DDR5/4/3L/3, to 6400Mbps and beyond

Overview

Today’s device users demand quick response time and high-resolution images that require electronics systems to process higher volumes of data and video, exploding the required capacity and bandwidth for device memory. The Cadence Denali DDR IP family of high-speed on-chip IP interfaces to external memories and provides the bandwidth necessary to support these applications.

The Cadence Denali Controller IP for LPDDR5/4X/4/3 and DDR5/4/3L/3 provides low latency and up to 5500Mbps throughput, while supporting extensive value-added features including, but not limited to, reliability features.

Developed by experienced teams with industry-leading domain expertise and validated with multiple hardware platforms, the Controller IP is silicon proven and can provide customers with ease of integration and faster time to market. 

The Controller IP is engineered to quickly and easily integrate into any system-on-chip (SoC), and is verified with the Denali DDR PHY IP as part of a complete memory subsystem solution which also includes Cadence Verification IP (VIP). The Controller IP is designed to connect seamlessly and work with a third-party, DFI-compliant DDR PHY IP.

The Controller IP is developed and validated to reduce risk for the customer, so that their SoC can be first-time right. Developed for and available in alignment with the PHY IP on advanced semiconductor process nodes, the Controller IP is designed to be robust under various traffic loads and to have interoperability with various supplier memory chips.

The Controller IP is part of the comprehensive Cadence Design IP portfolio comprised of interface, Denali memory interface, analog, and systems and peripherals IP.

Figure 1: Example system-level block diagram

Benefits

  • Configurable to meet specific data traffic profiles
  • Optimized low latency for data-intensive applications
  • Future-proof system design for emerging DDR standards

Product Details

The Controller IP is designed to provide the flexibility needed to enable application-specific configurations ranging from high-performance networking and mobile to consumer. The host-side port interface can be configured to support multiple ports, each of varying width and with different AMBA protocol and clocking options. The command queue intelligently schedules traffic from the port arbiter to maximize data throughput efficiency. The Controller IP includes various feature options such as low-power modes required by mobile applications and several reliability features required by enterprise applications.

Key Features

  • Compliant to LPDDR5/4X4/3 and DDR5/4/3L/3 protocol memories
  • Side-band or in-line ECC
  • Flexible paging policy including auto-prechargeper-command
  • Single and multi-port host interface options
  • Supports advanced RAS features including SEC/DED ECC, error scrubbing, parity, etc.
  • Priority-per command on Arm AMBA 3 AXI and low-latency Denali interface
  • QoS features allow command prioritization on Arm AMBA 4 AXI interfaces
  • Silicon proven and shipping in volume

DDR DRAM Controller

The Controller IP was engineered to be highly configurable, allowing the selection of application-specific features, which in turn yield an area-optimized solution per application. The controller is also developed to provide maximum throughput across many different traffic profiles.

The Controller IP uses multi-stage reordering algorithms architected for use with traffic profiles from many different applications. Performance-tuning parameters allow performance optimization based on individual system and memory requirements.

The Controller IP includes optional features to support high density system requirements including RDIMM and LRDIMM, as well as 3DS and x4 DRAM devices.

The Controller IP also delivers a wide array of capabilities to address emerging DDR DRAM subsystem reliability, availability, and serviceability (RAS) requirements. Some of these capabilities include embedded support for ECC and other vital error detection and error prevention capabilities, such as parity protection and DRAM data scrubbing. All of the Controller IP configurations support power-down and self-refresh. The optional advanced low-power module includes automatic power level stepping (based on traffic). This level of low-power support can significantly reduce standby and active power. A security option for addressrange protection is also available.

Figure 2: IP-level block diagram

Host Interface

The host interface natively supports any mix of AHB and AXI interfaces, up to 16 buses. Both priority-per-command on AMBA 3 AXI interfaces and QoS on AMBA 4 AXI interfaces improve latency and controller QoS, especially for transactions delivered through an interconnect fabric. Flexible synchronization allows low-latency synchronous port connection, reduced latency pseudo-synchronous ratio port connection, or highly flexible asynchronous port connection.

DFI Interface

The DFI-compliant PHY interface connects to Cadence or thirdparty hard and soft PHYs.

Availability

The Controller IP is available with various configurations and supports the following protocols:

Protocol Speed
DDR5/4 up to 5600Mbps
LPDDR5/4X up to 6400Mbps
LPDDR4X/4/3 up to 4266Mbps
DDR4/3L/3 up to 3200Mbps

Related Products

  • DDR Subsystem—integrated controller, PHY, and software 
  • GDDR6 Controller and PHY IP
  • HBM Controller and PHY IP
  • LPDDR/DDR Controller and PHY IP 
  • LPDDR Controller and PHY IP 
  • DDR Controller and PHY IP

Deliverables

  • Clean, readable, synthesizeable Verilog RTL 
  • Synthesis and STA scripts 
  • Documentation—integration and user guide, release notes 
  • Sample verification testbench with integrated BFM and monitors

For more information, visit Design IP.