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Cadence to Acquire AWR Corporation from National Instruments to Accelerate System Innovation for 5G RF Communications
Cadence Design Systems, Inc. and National Instruments Corporation announced that they have entered into a definitive agreement pursuant to which Cadence expects to acquire AWR Corporation, a wholly owned s...
02 Dec 2019
Allegro Package Designer Plus
The Cadence Allegro® platform offers complete and scalable technology for the design and implementation of PCBs and complex packages. Cadence IC package design technology allows designers to optimize compl...
1 MB
Backchannel Modeling and Simulation Using Recent Enhancements to the IBIS Standard White Paper
Recent enhancements to the upcoming IBIS standard now support backchannel training, enabling IBIS-AMI models to emulate this real-world SerDes behavior. AMI modelers now can incorporate backchannel algorit...
2 MB
Signal Integrity Methodology for Double-Digit Multi-Gigabit Interfaces
This paper will suggest methodologies for creating a “virtual prototype” of your serial link pre-design, and how to create the associated interconnect and SerDes models that go with it. We will review how ...
818 KB
Technical University of Braunschweig and Cadence Success Story
Technical University of Braunschweig (TUBS) is a public research university located in Braunschweig, in the Lower Saxonian region of northern Germany. TUBS is a member of the Cadence Academic Network.
317 KB
3D ICs with TSVs - Design Challenges and Requirements White Paper
A successful 3D IC design environment captures design intent up front, supports abstraction with early estimation and floorplanning, and achieves convergence through test, implementation, extraction, analy...
407 KB
Power-Aware Analysis Solution Whitepaper
By reviewing the classic (or traditional) signal integrity (SI) methodology, analyzing high-speed design flows, and examining what is employed in Cadence® Sigrity™ power and signal simulations using the SP...
442 KB
Virtuoso System Design Platform
The Cadence® Virtuoso® System Design Platform is a holistic, system-based solution that provides the functionality to drive simulation and LVS-clean layout of ICs and packages from a single schematic.
1 MB
Save Time and Minimize Errors by Automating Co-Design and Co-Analysis of Chips, Boards, and Packages
Cross-domain co-design and co-analysis capabilities are provided by the Cadence Virtuoso System Design Platform, which integrates IC design—including multiple heterogeneous die—into the Allegro and Sigrity...
3 MB
Allegro Package Designer Plus Silicon Layout Option
Fan-out wafer-level package (FOWLP) design places new demands on the IC backend and package substrate design teams and the design tools and flows that they use. The Cadence® Allegro® Package Designer Plus ...
364 KB
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