Resource Library

123 Result(s) Found Sort by Relevance Sort by Last Modified
Cadence to Acquire AWR Corporation from National Instruments to Accelerate System Innovation for 5G RF Communications Cadence Design Systems, Inc. and National Instruments Corporation announced that they have entered into a definitive agreement pursuant to which Cadence expects to acquire AWR Corporation, a wholly owned s... 02 Dec 2019
Backchannel Modeling and Simulation Using Recent Enhancements to the IBIS Standard White Paper Recent enhancements to the upcoming IBIS standard now support backchannel training, enabling IBIS-AMI models to emulate this real-world SerDes behavior. AMI modelers now can incorporate backchannel algorit... 2 MB
Signal Integrity Methodology for Double-Digit Multi-Gigabit Interfaces This paper will suggest methodologies for creating a “virtual prototype” of your serial link pre-design, and how to create the associated interconnect and SerDes models that go with it. We will review how ... 818 KB
Technical University of Braunschweig and Cadence Success Story Technical University of Braunschweig (TUBS) is a public research university located in Braunschweig, in the Lower Saxonian region of northern Germany. TUBS is a member of the Cadence Academic Network. 317 KB
3D ICs with TSVs - Design Challenges and Requirements White Paper A successful 3D IC design environment captures design intent up front, supports abstraction with early estimation and floorplanning, and achieves convergence through test, implementation, extraction, analy... 407 KB
Cadence OrbitIO Interconnect Designer Datasheet OrbitIO interconnect designer revolutionizes the system input/output (I/O) planning process by unifying chip, package, and board data in a single canvas environment where placement and connectivity scenari... 673 KB
Cadence Sigrity SystemSI Signal Integrity Solutions Datasheet Cadence Sigrity SystemSI signal integrity solutions provide a comprehensive and flexible SI analysis environment for accurately assessing high-speed, chip-to-chip system designs and support industry-standa... 518 KB
IBIS-AMI for SerDes Modeling Conference Paper IBIS-AMI is today's standard format for system-level SerDes modeling. Transistor-level accuracy can be combined with high-capacity channel simulation to predict BER using AMI modeling. 2 MB
Cadence Sigrity XtractIM Datasheet Cadence Sigrity XtractIM tool provides a complete model extraction environment focused specifically on IC package applications. The tool generates electrical models of IC packages in IBIS or SPICE circuit ... 461 KB
Using Power Aware IBIS v5.0 Behavioral IO Models to Simulate Simultaneous Switching Noise Conference Paper The power aware IBIS v5.0 behavioral models offer both dramatically faster transient simulation times and lower memory requirements. By Xilinx and Cadence 914 KB

Cadence to Acquire AWR Corporation from National Instruments to Accelerate System Innovation for 5G RF Communications

Cadence Design Systems, Inc. and National Instruments Corporation announced that they have entered into a definitive agreement pursuant to which Cadence expects to acquire AWR Corporation, a wholly owned s...

02 Dec 2019

Backchannel Modeling and Simulation Using Recent Enhancements to the IBIS Standard White Paper

Recent enhancements to the upcoming IBIS standard now support backchannel training, enabling IBIS-AMI models to emulate this real-world SerDes behavior. AMI modelers now can incorporate backchannel algorit...

2 MB

Signal Integrity Methodology for Double-Digit Multi-Gigabit Interfaces

This paper will suggest methodologies for creating a “virtual prototype” of your serial link pre-design, and how to create the associated interconnect and SerDes models that go with it. We will review how ...

818 KB

Technical University of Braunschweig and Cadence Success Story

Technical University of Braunschweig (TUBS) is a public research university located in Braunschweig, in the Lower Saxonian region of northern Germany. TUBS is a member of the Cadence Academic Network.

317 KB

3D ICs with TSVs - Design Challenges and Requirements White Paper

A successful 3D IC design environment captures design intent up front, supports abstraction with early estimation and floorplanning, and achieves convergence through test, implementation, extraction, analy...

407 KB

Cadence OrbitIO Interconnect Designer Datasheet

OrbitIO interconnect designer revolutionizes the system input/output (I/O) planning process by unifying chip, package, and board data in a single canvas environment where placement and connectivity scenari...

673 KB

Cadence Sigrity SystemSI Signal Integrity Solutions Datasheet

Cadence Sigrity SystemSI signal integrity solutions provide a comprehensive and flexible SI analysis environment for accurately assessing high-speed, chip-to-chip system designs and support industry-standa...

518 KB

IBIS-AMI for SerDes Modeling Conference Paper

IBIS-AMI is today's standard format for system-level SerDes modeling. Transistor-level accuracy can be combined with high-capacity channel simulation to predict BER using AMI modeling.

2 MB

Cadence Sigrity XtractIM Datasheet

Cadence Sigrity XtractIM tool provides a complete model extraction environment focused specifically on IC package applications. The tool generates electrical models of IC packages in IBIS or SPICE circuit ...

461 KB

Using Power Aware IBIS v5.0 Behavioral IO Models to Simulate Simultaneous Switching Noise Conference Paper

The power aware IBIS v5.0 behavioral models offer both dramatically faster transient simulation times and lower memory requirements. By Xilinx and Cadence

914 KB

Resource Library

Filter Results: