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How ML Enables Cadence Digital Tools to Deliver Better PPA
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Overcoming PPA and Productivity Challenges of New Age ICs with Mixed Placement InnovationInnovus White Paper, Innovus Mixed Placer, Mixed Placement
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How to Achieve Optimal PPA and Up to 10X TAT Gain in Your Next Digital Design Implementation White PaperThis paper discusses new digital implementation technology that equips you to handle larger size blocks and meet stringent PPA and TAT goals for SoCs at advanced 16/14/10nm FinFET as well as established pr...
385 KB
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Better PPA with Innovus Mixed Placer Technology – Gigaplace XLWith data-centric designs demanding increases in the number of on-chip storage elements, the area occupied by macros and memories has also drastically increased. With the number of rectangular macros going...
20 Oct 2020
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Cadence Digital Full Flow Optimized to Deliver Improved Quality of Results with Up to 3X Faster ThroughputCadence announced that the new release of the Cadence digital full flow—proven with hundreds of completed advanced-node tapeouts—has been enhanced to further optimize power, performance and area (PPA) resu...
17 Mar 2020
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Cadence Achieves Digital and Custom/Analog EDA Flow Certification for TSMC N6 and N5 Process TechnologiesCadence announced that its digital full flow and custom/analog tool suites have been further enhanced to deliver optimal results on TSMC’s N6 and N5 process technologies.
02 Jun 2020
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Pushing frequency, power and area with the iSpatial flow to achieve Design ExcellenceYufeng Luo, VP Research and Development at Cadence talks about new innovations in the Cadence digital implementation flow which are helping customers meet or exceed Power, Performance and Area targets on c...
05 Mar 2020
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GigaPlace Solver-Based Placement Technology In Innovus Implementation SystemThe GigaPlace engine in Cadence's Innovus™ Implementation System provides optimal pipeline placement, wire length, utilization, and power, performance, and area (PPA). See how GigaPlace , with its breakthr...
06 Dec 2018
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Cadence Reference Flow with Digital and Signoff Tools Certified on Samsung’s 10nm Process TechnologyCadence today announced that its complete suite of digital and signoff tools has been certified for Samsung's PDK and Foundation Library on the second-generation of Samsung’s 10nm LPP process.
24 Oct 2016
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Cadence Tools and Flows Achieve Production-Ready Certification for TSMC’s 12FFC ProcessCadence announced that its digital, signoff and custom/analog tools and flows have achieved v1.0 certification for TSMC’s 12nm FinFET Compact (12FFC) process technology and are production ready for custome...
11 Sep 2017
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