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Cadence Achieves Digital and Custom/Analog EDA Flow Certification for TSMC N6 and N5 Process TechnologiesCadence announced that its digital full flow and custom/analog tool suites have been further enhanced to deliver optimal results on TSMC’s N6 and N5 process technologies.
02 Jun 2020
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Cadence Digital Full Flow Optimized to Deliver Improved Quality of Results with Up to 3X Faster ThroughputCadence announced that the new release of the Cadence digital full flow—proven with hundreds of completed advanced-node tapeouts—has been enhanced to further optimize power, performance and area (PPA) resu...
17 Mar 2020
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Pushing frequency, power and area with the iSpatial flow to achieve Design ExcellenceYufeng Luo, VP Research and Development at Cadence talks about new innovations in the Cadence digital implementation flow which are helping customers meet or exceed Power, Performance and Area targets on c...
05 Mar 2020
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GigaPlace Solver-Based Placement Technology In Innovus Implementation SystemThe GigaPlace engine in Cadence's Innovus™ Implementation System provides optimal pipeline placement, wire length, utilization, and power, performance, and area (PPA). See how GigaPlace , with its breakthr...
06 Dec 2018
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Cadence Reference Flow with Digital and Signoff Tools Certified on Samsung’s 10nm Process TechnologyCadence today announced that its complete suite of digital and signoff tools has been certified for Samsung's PDK and Foundation Library on the second-generation of Samsung’s 10nm LPP process.
24 Oct 2016
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Cadence Tools and Flows Achieve Production-Ready Certification for TSMC’s 12FFC ProcessCadence announced that its digital, signoff and custom/analog tools and flows have achieved v1.0 certification for TSMC’s 12nm FinFET Compact (12FFC) process technology and are production ready for custome...
11 Sep 2017
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eInfochips Shortens Runtime on 300M Gate Count SoCs with Innovus Implementation SystemDesigning a large-scale SoC? Watch this 3-minute video to hear Nilesh Ranpura, a project manager at eInfochips, and Dhaval Parikh, sr. tech lead, physical design, shortened runtime and improved productivit...
08 Mar 2016
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Addressing Body Biasing Challenges at GLOBALFOUNDRIESHear Herbert Preuthen of GLOBALFOUNDRIES's MTS Design Engineering team discuss how they addressed the challenges that body biasing brought to implementation of their 22FDX FD-SOI technology. The company ov...
25 Jul 2016
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Reducing Design Flow Iterations with GigaPlace EngineThe GigaPlace engine in Cadence's Innovus™ Implementation System employs some powerful techniques to reduce implementation flow iterations. Learn how some of the new techniques in GigaPlace help reduce cos...
29 May 2016
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Tackling 16nm Challenges for Arm Cortex-A72 ProcessorIn this 2-minute video, McKanna talks about how Arm and Cadence worked together to address the challenges of developing the Arm Cortex-A72 processor at 16nm. See how the teams overcame the challenges, usin...
17 Sep 2015
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