- Innovus Implementation System (13)
- Innovus Implementation Solution (13)
- Digital Design and Signoff (10)
- Hierarchical Design and Floor Planning (10)
- Block Implementation (8)
- Tempus Timing Signoff Solution (6)
- Quantus QRC Extraction (5)
- Genus Synthesis Solution (4)
- Silicon Signoff (4)
- Voltus IC Power Integrity Solution (4)
- Synthesis (3)
- Virtuoso Liberate (2)
- Virtuoso ADE Product Suite (2)
- Virtuoso Schematic Editor (2)
- Flows (2)
- Conformal Low Power (2)
- Physical Verification System (2)
- Voltus-Fi Custom Power Integrity Solution (2)
- Virtuoso Liberate AMS (1)
- Virtuoso Liberate LV (1)
- Virtuoso Liberate MX (1)
- Virtuoso Variety (1)
- Virtuoso ADE Assembler (1)
- Virtuoso ADE Explorer (1)
- Process Variation Modeling (1)
- Virtuoso ADE Verifier (1)
- Virtuoso Analog Design Environment (1)
- Virtuoso Layout Suite for Electrically Aware Design (1)
- Spectre Accelerated Parallel Simulator (1)
- Spectre Circuit Simulator (1)
- Spectre eXtensive Partitioning Simulator (XPS) (1)
- Spectre RF Option (1)
- Virtuoso RF Solution (1)
- Virtuoso Layout Suite (1)
- Virtuoso Integrated Physical Verification System (1)
- Conformal Overview (1)
- Equivalence Checker (1)
- Arm-based Designs (1)
- Low Power Validation (1)
- CMP Predictor (1)
- LDE Electrical Analyzer (1)
- Litho Physical Analyzer (1)
- Pegasus Verification System (1)
- Liberate Trio Characterization Suite (1)
- Characterization (1)
- Library Validation (1)
- Spectre Circuit Simulator (1)
- Test (1)
- Modus Test Solution (1)
Cadence Achieves Digital and Custom/Analog EDA Flow Certification for TSMC N6 and N5 Process Technologies
Cadence announced that its digital full flow and custom/analog tool suites have been further enhanced to deliver optimal results on TSMC’s N6 and N5 process technologies.
02 Jun 2020
Cadence Digital Full Flow Optimized to Deliver Improved Quality of Results with Up to 3X Faster Throughput
Cadence announced that the new release of the Cadence digital full flow—proven with hundreds of completed advanced-node tapeouts—has been enhanced to further optimize power, performance and area (PPA) resu...
17 Mar 2020
Yufeng Luo, VP Research and Development at Cadence talks about new innovations in the Cadence digital implementation flow which are helping customers meet or exceed Power, Performance and Area targets on c...
05 Mar 2020
The GigaPlace engine in Cadence's Innovus™ Implementation System provides optimal pipeline placement, wire length, utilization, and power, performance, and area (PPA). See how GigaPlace , with its breakthr...
06 Dec 2018
Cadence Reference Flow with Digital and Signoff Tools Certified on Samsung’s 10nm Process Technology
Cadence today announced that its complete suite of digital and signoff tools has been certified for Samsung's PDK and Foundation Library on the second-generation of Samsung’s 10nm LPP process.
24 Oct 2016
Cadence announced that its digital, signoff and custom/analog tools and flows have achieved v1.0 certification for TSMC’s 12nm FinFET Compact (12FFC) process technology and are production ready for custome...
11 Sep 2017
Designing a large-scale SoC? Watch this 3-minute video to hear Nilesh Ranpura, a project manager at eInfochips, and Dhaval Parikh, sr. tech lead, physical design, shortened runtime and improved productivit...
08 Mar 2016
Hear Herbert Preuthen of GLOBALFOUNDRIES's MTS Design Engineering team discuss how they addressed the challenges that body biasing brought to implementation of their 22FDX FD-SOI technology. The company ov...
25 Jul 2016
The GigaPlace engine in Cadence's Innovus™ Implementation System employs some powerful techniques to reduce implementation flow iterations. Learn how some of the new techniques in GigaPlace help reduce cos...
29 May 2016
In this 2-minute video, McKanna talks about how Arm and Cadence worked together to address the challenges of developing the Arm Cortex-A72 processor at 16nm. See how the teams overcame the challenges, usin...
17 Sep 2015