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226 Result(s) Found
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Compressing Datasets Created During Silicon Design White PaperCompressing Datasets Created During Silicon Design
By Guru Rao, Distinguished Engineer; Shakir Abbas, Software Engineering Group Director;
Mohammad Mirfendereski, Configuration …
137 KB
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Quantus Extraction SolutionThe Cadence® Quantus™ Extraction Solution is a next-generation parasitic extraction tool for digital and custom/analog flows, providing the fastest performance and scalability and best-in-class accuracy us...
570 KB
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Conformal Smart LECCadence® Conformal® Smart LEC is the next-generation equivalence checking solution. Offering key technologies of massive parallelism and adaptive proof, Conformal Smart LEC improves runtime by an average o...
226 KB
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Quantus Smart View—Next-Generation Extracted ViewCadence® Quantus™ Smart View is the next generation of the current market-leading Extracted View, a flow that Cadence pioneered over a decade ago for faster circuit debugging and post-layout verification a...
2 MB
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Unified Compression and LBIST in a Physically Aware EnvironmentUnified compression scans and LBIST leverages DFT to solve routing congestion and area issues.
462 KB
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Quantus FS—Industry’s First Cloud-Ready, Massively Parallel 3D Extraction SolutionThe Cadence® Quantus™ FS (Field Solver) Solution is a built-in 3D capacitance field solver offered with the Quantus Extraction Solution. This random-walk-based field solver can handle any capacity, provide...
609 KB
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SPIE 2017: Pattern-Based Analytics to Estimate and Track Yield Risk of Designs Down to 7nm Conference PaperTopological pattern-based methods for analyzing IC physical design complexity and scoring resulting patterns to identify risky patterns have emerged as powerful tools for identifying important trends and c...
1 MB
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SPIE 2017: Methodology for Analyzing and Quantifying Design Style Changes and Complexity Using Topological Patterns Conference PaperThis paper introduces a novel methodology for full chip high performance topological pattern analysis and the applications of this methodology towards analyzing design styles in order to quantify and measu...
1 MB
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Pattern-Based Analytics to Estimate and Track Yield Risk of Designs Down to 7nm Conference PresentationPattern-based analytics to estimate and
track yield risk of designs down to 7nm
JASON CAIN, MOUTAZ FAKHRY (AMD)
PIYUSH PATHAK, JASON SWEIS, PHILIPPE HURAT, YA-CHIEH LAI …
1 MB
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Methodology for Analyzing and Quantifying Design Style Changes and Complexity Using Topological Patterns Conference PresentationMETHODOLOGY FOR ANALYZING AND
QUANTIFYING DESIGN STYLE CHANGES AND
COMPLEXITY USING TOPOLOGICAL PATTERNS
1 2 2 2
JASON CAIN , YA-CHIEH LAI , FRANK GENNARI , JASON SWEIS
1 2 …
898 KB
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