- Digital Design and Signoff (171)
- Innovus Implementation System (74)
- Tempus Timing Signoff Solution (61)
- Silicon Signoff (58)
- Quantus QRC Extraction (53)
- Voltus IC Power Integrity Solution (44)
- Genus Synthesis Solution (38)
- Block Implementation (36)
- Synthesis (33)
- Modus Test Solution (30)
- Test (22)
- Physical Verification System (22)
- Voltus-Fi Custom Power Integrity Solution (21)
- Hierarchical Design and Floor Planning (17)
- Virtuoso Layout Suite (14)
- Custom IC - Analog - RF Design (14)
- Conformal Low Power (14)
- Innovus Implementation Solution (13)
- System Design and Verification (13)
- Stratus High-Level Synthesis (11)
- Spectre Accelerated Parallel Simulator (10)
- CMP Predictor (9)
- LDE Electrical Analyzer (9)
- Liberate Trio Characterization Suite (9)
- Pegasus Verification System (9)
- Equivalence Checker (9)
- Spectre Circuit Simulator (9)
- Virtuoso ADE Product Suite (9)
- Virtuoso Schematic Editor (9)
- Flows (9)
- Joules RTL Power Solution (9)
- Spectre eXtensive Partitioning Simulator (XPS) (8)
- Litho Physical Analyzer (8)
- Virtuoso Liberate (8)
- Conformal ECO Designer (7)
- Conformal Overview (7)
- Circuit Simulation (6)
- Characterization (6)
- Virtuoso Liberate AMS (6)
- Low Power Validation (6)
- Functional ECO (6)
- Virtuoso Liberate MX (6)
- Virtuoso Variety (5)
- Layout Verification (5)
- Virtuoso ADE Assembler (5)
- Virtuoso ADE Explorer (5)
- Process Variation Modeling (5)
- Library Validation (5)
- MaskCompose Reticle and Wafer Synthesis Suite (5)
- Virtuoso ADE Verifier (5)
- Quickview Signoff Data Analysis Environment (5)
- Virtuoso Analog Design Environment (5)
- Virtuoso Layout Suite for Electrically Aware Design (5)
- OrbitIO Interconnect Designer (5)
- Sigrity PowerDC (5)
- Virtuoso Liberate LV (5)
- Spectre RF Simulation (4)
- Library Characterization (4)
- IC Package Design and Analysis (4)
- Pattern Analysis (4)
- SiP Layout (4)
- SiP Layout WLCSP (4)
- Allegro Package Designer (4)
Cadence revolutionized the way digital designers could solve their design challenges by revamping the entire digital tool suite with key enhancements such as integrated engines, massively parallel processi...
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Cadence® Quantus™ Smart View is the next generation of the current market-leading Extracted View, a flow that Cadence pioneered over a decade ago for faster circuit debugging and post-layout verification a...
Unified compression scans and LBIST leverages DFT to solve routing congestion and area issues.
The Cadence® Quantus™ Extraction Solution is a next-generation parasitic extraction tool for digital and custom/analog flows, providing the fastest performance and scalability and best-in-class accuracy us...
Cadence® Conformal® Smart LEC is the next-generation equivalence checking solution. Offering key technologies of massive parallelism and adaptive proof, Conformal Smart LEC improves runtime by an average o...
The design, implementation, and verification tools and flows provided by Cadence address all areas of power management and solve the SoC low-power problem.
A successful 3D IC design environment captures design intent up front, supports abstraction with early estimation and floorplanning, and achieves convergence through test, implementation, extraction, analy...
Interactive Short Locator: Establishing Efficiency and Predictability in the LVS Short Debug Process for Advanced SoC Designs Technical Paper
Interactive Short Locator technology in the Cadence Physical Verification System provides an efficient debug solution that employs a dedicated analysis engine and interactive workflow to locate shorts quic...
Genus Synthesis Solution is a next-generation RTL synthesis and physical synthesis tool that delivers an up to 10X boost in RTL design productivity with up to 5X faster turnaround times.