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Cadence and National Instruments Enter into Strategic Alliance Agreement to Enhance Electronic System InnovationNational Instruments Corporation and Cadence Design Systems, Inc. announced a system innovation strategic alliance to create an integrated design to test flow, leveraging reusable data and test IP from ele...
02 Dec 2019
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Cadence to Acquire AWR Corporation from National Instruments to Accelerate System Innovation for 5G RF CommunicationsCadence Design Systems, Inc. and National Instruments Corporation announced that they have entered into a definitive agreement pursuant to which Cadence expects to acquire AWR Corporation, a wholly owned s...
02 Dec 2019
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Addressing the Challenges of Photonic IC Design Via an Integrated Electronic/Photonic Design Automation Environment, Addressing the Challenges of Photonic IC Design Via an Integrated Electronic/Photonic Design Automation Environment White PaperIn this paper, we examine how a new integrated electronic/photonic design automation (EPDA) environment solves the challenges of layout, error checking, and circuit modeling, and supports first-time-right ...
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Virtuoso Layout Suite GXL DatasheetVirtuoso Layout Suite GXL is the fully automated custom placement, routing, layout optimization, module generation, and floorplanning environment of the Virtuoso custom design platform.
1 MB
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Virtuoso Layout Suite L DatasheetVirtuoso Layout Suite L is a base-level custom physical layout environment focused on boosting productivity. It supports custom analog, digital, RF, and mixed-signal designs at the device, cell, block, and...
749 KB
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Virtuoso Layout Suite for Electrically Aware Design DatasheetVirtuoso Layout Suite (VLS) for Electrically Aware Design enables the electrically correct-by-construction layout. With this solution, one can electrically analyze, simulate, and verify interconnect decisi...
1 MB
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Cadence Custom/AMS Flow Certified for Samsung 5LPE Process TechnologyCadence today announced that its custom and AMS IC design flow has achieved certification for Samsung Foundry’s 5nm Low-Power Early (5LPE) process technology.
17 Oct 2019
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Cadence Achieves EDA Certification for TSMC 5nm and 7nm+ FinFET Process Technologies to Facilitate Mobile and HPC Design CreationCadence announced its continued collaboration with TSMC to certify its design solutions for TSMC 5nm and 7nm+ FinFET process technologies for mobile and high-performance computing (HPC) designs.
01 Oct 2018
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Cadence Custom/AMS Flow Certified on Samsung 7LPP Process TechnologyCadence custom and analog/mixed-signal (AMS) IC design tools have achieved certification for Samsung Foundry’s 7nm Low Power Plus (7LPP) process technology
23 Oct 2018
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Cadence Collaborates with TSMC to Accelerate 5nm FinFET Innovation, Enabling Next-Generation SoC Production DesignCadence announced that it has collaborated with TSMC to enable customers’ production delivery of next-generation SoC designs for mobile, HPC, 5G and AI applications on TSMC’s 5nm FinFET process technology.
22 Apr 2019
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