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36 Result(s) Found
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Virtuoso Layout Suite for Electrically Aware Design DatasheetVirtuoso Layout Suite (VLS) for Electrically Aware Design enables the electrically correct-by-construction layout. With this solution, one can electrically analyze, simulate, and verify interconnect decisi...
1 MB
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Virtuoso Layout Suite GXL DatasheetVirtuoso Layout Suite GXL is the fully automated custom placement, routing, layout optimization, module generation, and floorplanning environment of the Virtuoso Layout Suite platform.
1 MB
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Addressing the Challenges of Photonic IC Design Via an Integrated Electronic/Photonic Design Automation Environment, Addressing the Challenges of Photonic IC Design Via an Integrated Electronic/Photonic Design Automation Environment White PaperIn this paper, we examine how a new integrated electronic/photonic design automation (EPDA) environment solves the challenges of layout, error checking, and circuit modeling, and supports first-time-right ...
1 MB
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Virtuoso Layout Suite L DatasheetVirtuoso Layout Suite L is a base-level custom physical layout environment focused on boosting productivity. It supports custom analog, digital, RF, and mixed-signal designs at the device, cell, block, and...
749 KB
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Cadence and National Instruments Enter into Strategic Alliance Agreement to Enhance Electronic System InnovationNational Instruments Corporation and Cadence Design Systems, Inc. announced a system innovation strategic alliance to create an integrated design to test flow, leveraging reusable data and test IP from ele...
02 Dec 2019
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Cadence to Acquire AWR Corporation from National Instruments to Accelerate System Innovation for 5G RF CommunicationsCadence Design Systems, Inc. and National Instruments Corporation announced that they have entered into a definitive agreement pursuant to which Cadence expects to acquire AWR Corporation, a wholly owned s...
02 Dec 2019
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Cadence Custom/AMS Flow Certified for Samsung 5LPE Process TechnologyCadence today announced that its custom and AMS IC design flow has achieved certification for Samsung Foundry’s 5nm Low-Power Early (5LPE) process technology.
17 Oct 2019
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Virtuoso Design Platform for Next-Generation Custom IC and System DesignThe Virtuoso Design Platform addresses the advanced design environment challenges faced by today’s design engineers. Smart products are becoming very highly integrated with multiple components all on the s...
30 Aug 2019
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Meeting the Challenges of Chip Design Using the Virtuoso SuiteAtul Bhargava of STMicroelectronics discusses how the Cadence Virtuoso Design Platform meets their challenges of matching devices and parasitics, mixed-signal implementation, and full-chip time to closure.
25 Jul 2019
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Toshiba Electronic Device Solutions Overcomes Complexities of Advanced-Node DesignsAdvanced-node technologies continue to get more complex, making it difficult to apply the same technical guesswork used for legacy nodes. Learn how Toshiba Electronic Device Solutions Corporation (TEDS) us...
13 Aug 2019
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