- Power-Aware Verification Methodology (14)
- System Design and Verification (13)
- Flows SDV (12)
- Palladium XP Series (4)
- Conformal Low Power (3)
- Palladium Dynamic Power Analysis (3)
- JaperGold Verification Platform (3)
- Simulation and Testbench Verification (3)
- Incisive Enterprise Simulator (3)
- Circuit Design (2)
- Virtuoso AMS Designer (2)
- Digital Design and Signoff (2)
- Innovus Implementation System (2)
- Flows (2)
- Low Power Validation (2)
- Acceleration and Emulation (2)
- Formal and Static Verification (2)
- Custom IC - Analog - RF Design (1)
- Virtuoso ADE Assembler (1)
- Virtuoso ADE Explorer (1)
- Virtuoso ADE Product Suite (1)
- Virtuoso ADE Verifier (1)
- Virtuoso Analog Design Environment (1)
- Virtuoso Schematic Editor (1)
- Circuit Simulation (1)
- AMS Designer (1)
- Spectre Accelerated Parallel Simulator (1)
- Spectre Circuit Simulator (1)
- Spectre RF Simulation (1)
- Virtuoso Layout Suite (1)
- Layout Verification (1)
- RF Design (1)
- Block Implementation (1)
- Low Power (1)
- Quantus QRC Extraction (1)
- Tempus Timing Signoff Solution (1)
- Voltus-Fi Custom Power Integrity Solution (1)
- Voltus IC Power Integrity Solution (1)
- Palladium Z1 Series (1)
- Genus Synthesis Solution (1)
- Debug Analysis (1)
- Incisive Formal Verification Platform (1)
- Software-driven Verification (1)
The design, implementation, and verification tools and flows provided by Cadence address all areas of power management and solve the SoC low-power problem.
To examine simulation and emulation technologies for a thorough, yet faster functional verification of low-power systems on chip (SoCs), this paper first reviews the fundamental sources and reduction techn...
By combining Palladium XP DPA with Encounter Power System TI achieved close correlation between the architects power estimation and actual silicon power consumption measurements enabling the company to del...
Cadence technology enables Silicon Labs to accelerate delivery of energy-efficient Blue Gecko Bluetooth Smart SoCs to the IoT market
24 Feb 2016
Sathya Subramanian Low Power Summit 2012 discussion on ARM's perspective on Low Power Design techiques and Physical IP, Architecture Optimization, Cell Level, optimizing power at multiple levels, Factors i...
22 Aug 2015
Adam Sherer and Mickey Rodriguez discuss Introducing Low Power Verification RAK. Topics in this discussion are Cadence Low Power Verification, Setting up Low Power Verification, a demostration on Introduct...
22 Aug 2015
Kenneth Wagner PMC discusses Motivation, Vicious/Virtuous Cycle, Cadence Low Power Ecosystem, Cadence inCyte Chip Estimator. Kenneth Wagner decribes what is reasonable device/ system power estimation Accur...
22 Aug 2015
Watch this 2-minute video to hear Melanie Wilhelm, explain how the company revamped its low-power design flow using CPF to enable its customers to implement low-power functionality. Cadence's support, desi...
18 Mar 2016
Hear from Angela Liang, Sr. Mixed-Signal Verification Engineer, at Freescale Semiconductor as she describes how they utilized the Cadence Low Power and Mixed-Signal Solution to verify the company's Kinetis...
24 Jun 2016
Dr. Anthony R Simon at CSR discusses Five Platforms for Growth Automotive, Bluetooth Smart Low Power, Bluetooth Smart Applications examples, Next Generation of Internet Devices, Imaging, Location, Voice an...
22 Aug 2015