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Cadence and National Instruments Enter into Strategic Alliance Agreement to Enhance Electronic System InnovationNational Instruments Corporation and Cadence Design Systems, Inc. announced a system innovation strategic alliance to create an integrated design to test flow, leveraging reusable data and test IP from ele...
02 Dec 2019
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New Virtuoso Design Platform
4 MB
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Improved Analog Layout Productivity Using ModGen Template-Driven Layout Reuse Methodology in Virtuoso EnvironmentDevice level pattern planning, placement and routing of the matched structure is an important phase of full custom analog layout development. Matched devices are extensively used in analog designs, such as...
07 Jan 2021
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Cadence Wins Four 2020 TSMC OIP Partner of the Year AwardsCadence today announced that it has received four OIP Partner of the Year awards from TSMC for IP and EDA solutions for joint development of the N3 design infrastructure, 3D-IC design productivity solution...
02 Nov 2020
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Cadence Digital and Custom Flows Achieve Certification for TSMC N3 ProcessCadence announced that its digital full flow and custom tool suite has been optimized for TSMC’s 3nm (N3) process technology.
25 Aug 2020
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Cadence Achieves Digital and Custom/Analog EDA Flow Certification for TSMC N6 and N5 Process TechnologiesCadence announced that its digital full flow and custom/analog tool suites have been further enhanced to deliver optimal results on TSMC’s N6 and N5 process technologies.
02 Jun 2020
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Avoid Density Gradient Effects in 16FF+ Designs with Virtuoso Layout Suite GXL ModGensLearn how to use parameterizable modules created by Cadence and TSMC to effectively manage density gradient effects and layout complexity at 16FF+. You can design with a TSMC verified set of FinFET-based a...
15 Jul 2020
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Advanced Methodologies to Accelerate Your Custom LayoutThe custom layout process is a critical aspect of achieving your analog decision goals in terms of performance, die area, and tapeout date. Watch this webinar to learn about enhanced layout planning to opt...
26 Aug 2020
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Improve Device Matching with Assisted Component P&RThe increased analog content of today’s ICs needs more automation and reuse during the custom layout process. These circuits frequently use structures requiring precise matching of device characteristics.M...
26 Aug 2020
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Cadence Digital and Signoff Full Flow and Custom/Analog Tools Certified for TSMC N6 and N5/N5P Process TechnologiesCadence announced that its digital and signoff full flow and custom/analog tools have achieved certification on TSMC’s N6 and N5/N5P process technologies.
25 Sep 2019
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